7 All check switches to program 7 alteration switches 7 911- bypass error 7 typeouts and halts 7 912- loop in routine 7 913- halt out error 7 914- loop in program 7 915- bypass forced errors 7 916- channel operation 00004 sel 2 0500 00009 wr r 0095 typeout switch settings 00014 hlt j 1111 00019 eem 3 14 0000 0+-0 enter 7080 mode 00024 chr 3 13 0000 0+ 0 and reset 00029 lim , 07 0000 0 +0 channels 00034 chr 3 13 0000 0+ 0 00039 trs o 09 0044 0-u4 turn 00044 trs o 10 0049 0-m9 off 00049 trs o 11 0054 0-e4 all 00054 trs o 12 0059 0+59 check 00059 trs o 13 0064 0+w4 triggers 00064 trs o 14 0069 0+o9 00069 trs o 15 0074 0+g4 00074 tra i 0079 00079 lem 3 15 0000 0++0 leave 7080 mode 00084 tr 1 0404 transfer to test routines 00089 hlt j 0000 safety halt after initial 00094 tr 1 0404 transfer 7 2 030 00124 900, 1, 2, 3, 4, 5 to program 2 001 00125 | 7 7 check trigger 7 sub-routine 7 interrogate and turn off 7 all cpu check triggers. 7 00204 lda = 0309 put ic location at time 00209 set b 0006 of check into typeout 00214 unl 7 0396 00219 set b 0003 set acc to 3 positions 00224 tra i 0229 turn off any 7 00229 eem 3 14 0000 0+-0 00234 lod 8 0352 00239 trs o 09 0314 0l/4 test art 00244 lod 8 0355 00249 trs o 10 0314 0lj4 test 900 00254 lod 8 0358 00259 trs o 11 0314 0la4 test 901 00264 lod 8 0361 00269 trs o 12 0314 0c14 test 902 00274 lod 8 0364 00279 trs o 13 0314 0c/4 test 903 00284 lod 8 0367 00289 trs o 14 0314 0cj4 test 904 00294 lod 8 0370 00299 trs o 15 0314 0ca4 test 905 7 00304 lem 3 15 0000 0++0 00309 tr 1 0000 return transfer 7 00314 tra i 01 0349 03u9 00319 unl 7 0373 00324 sel 2 0500 00329 wr r 0371 do typeout 00334 tra i 03 0344 03d4 00339 tr 1 0349 00344 nop a 0999 00349 tr 1 0229 7 2 021 00370 art900901902903904905 2 026 00396 --- chk prior to ic-000000 2 001 00397 | 7 7 routine #001 7 execute eem,cno,and trs. 7 test 900 check. 7 00404 eem 3 14 0000 0+-0 00409 cno , 11 66666 oofo set iar,mac-1 to 66666 00414 cno , 11 0000 0-+0 00419 cno , 11 99999 zriz set iar,mac-1 to 99999 00424 trs o 10 0434 0ml4 00429 tr 1 0464 7 00434 tra i 01 0464 04w4 error routine 00439 sel 2 0500 00444 wr r 0470 00449 tra i 03 0459 04e9 00454 tr 1 0464 00459 hlt j 0001 00464 tra i 02 0404 04-4 00469 tr 1 0479 7 2 003 00472 001 2 001 00473 | 7 7 routine #002 7 execute lem,sel,and nop. 7 test 900 check 00479 lem 3 15 0000 0++0 00484 nop a 15 0000 0++0 set ssr all on 00489 nop a 0000 00494 sel 2 6666 set sel reg to 6666 00499 nop a 0000 00504 sel 2 9999 set sel reg to 9999 00509 sel 2 0000 00514 sel 2 0900 00519 trs o 0529 00524 tr 1 0559 7 00529 tra i 01 0559 05v9 error routine 00534 sel 2 0500 00539 wr r 0565 00544 tra i 03 0554 05e4 00549 tr 1 0559 00554 hlt j 0002 00559 tra i 02 0479 04p9 00564 tr 1 0574 7 2 003 00567 002 2 001 00568 | 7 7 routine #003 7 execute rcv and spc. 7 test 900 check 7 00574 eem 3 14 0000 0+-0 00579 rcv u 66666 o66o set mac-2 to 66666 00584 rcv u 0000 00589 rcv u 99999 z99z set mac-2 to 99999 00594 rcv u 0000 00599 spc , 7737 set spc all on 00604 nop a 0000 set sac all on 00609 spc , 0000 00614 trs o 10 0624 0ok4 00619 tr 1 0654 7 00624 tra i 01 0654 06v4 error routine 00629 sel 2 0500 00634 wr r 0660 00639 tra i 03 0649 06d9 00644 tr 1 0654 00649 hlt j 0003 00654 tra i 02 0574 05p4 00659 tr 1 0669 7 2 003 00662 003 2 001 00663 | 7 00669 eem 3 14 0000 0+-0 routine #004 00674 trs o 09 0679 0ox9 turn off all alu check 00679 trs o 10 0684 0oq4 triggers and then test 00684 trs o 11 0689 0oh9 for false checks or 00689 trs o 12 0694 0f94 false transfers. 00694 trs o 13 0699 0fz9 00699 trs o 14 0704 0g-4 00704 trs o 15 0709 0g+9 7 00709 nop a 0000 test 00714 trs o 09 0754 0pv4 art error 00719 trs o 10 0754 0pn4 900 error 00724 trs o 11 0754 0pe4 901 error 00729 trs o 12 0754 0g54 902 error 00734 trs o 13 0754 0gv4 903 error 00739 trs o 14 0754 0gn4 904 error 00744 trs o 15 0754 0ge4 905 error 00749 tr 1 0784 7 00754 tra i 01 0784 07y4 error routine 00759 sel 2 0500 00764 wr r 0790 00769 tra i 03 0779 07g9 00774 tr 1 0784 00779 hlt j 0004 00784 tra i 02 0669 06o9 00789 tr 1 0799 7 2 003 00792 004 2 001 00793 | 7 7 routine #005 7 execute tzb and test for 7 false transfer or 900,9001 7 checks. 7 00799 lem 3 15 0000 0++0 00804 rcv u 0874 00809 tzb . 0834 error 00814 tzb . 15 0834 0hc4 error 00819 trs o 10 0834 0ql4 error 00824 trs o 11 0834 0qc4 error 00829 tr 1 0864 7 00834 tra i 01 0864 08w4 error routine 00839 sel 2 0500 00844 wr r 0871 00849 tra i 03 0859 08e9 00854 tr 1 0864 00859 hlt j 0005 00864 tra i 02 0799 07r9 00869 tr 1 0879 7 2 004 00873 005 2 001 00874 | 7 7 routine #006 7 use rcv-tzb to test for 7 ba8421 bits in mbr char 0 00879 rcv u 0970 00884 tzb . 07 0894 0yi4 00889 tr 1 0934 error 00894 trs o 11 0934 0rc4 error 00899 tzb . 01 0934 09t4 error 00904 tzb . 02 0934 09l4 error 00909 tzb . 03 0934 09c4 error 00914 tzb . 04 0934 0z34 error 00919 tzb . 05 0934 0zt4 error 00924 tzb . 06 0934 0zl4 error 00929 tr 1 0964 7 00934 tra i 01 0964 09w4 error routine 00939 sel 2 0500 00944 wr r 0975 00949 tra i 03 0959 09e9 00954 tr 1 0964 00959 hlt j 0006 00964 tra i 02 0879 08p9 00969 tr 1 0984 to next routine 7 2 001 00970 | 2 004 00974 1111 2 003 00977 006 2 001 00978 | 7 7 routine #007 7 use rcv-tzb to test for 7 ba8421 bits in mbr char 1. 7 00984 rcv u 1076 00989 tzb . 07 0999 0zi9 error 00994 tr 1 1039 error 00999 trs o 11 1039 1-c9 error 01004 tzb . 01 1039 10t9 error 01009 tzb . 02 1039 10l9 error 01014 tzb . 03 1039 10c9 error 01019 tzb . 04 1039 1 39 error 01024 tzb . 05 1039 1 t9 error 01029 tzb . 06 1039 1 l9 error 01034 tr 1 1069 7 01039 tra i 01 1069 10w9 error routine 01044 sel 2 0500 01049 wr r 1080 01054 tra i 03 1064 10f4 01059 tr 1 1069 01064 hlt j 0007 01069 tra i 02 0984 09q4 01074 tr 1 1089 7 2 001 01075 1 2 001 01076 | 2 003 01079 111 2 003 01082 007 2 001 01083 | 7 7 routine #008 7 use rcv-tzb to test for 7 ba8421 bits in mbr char 2. 7 01089 rcv u 1182 01094 tzb . 07 1104 1/+4 error 01099 tr 1 1144 error 01104 trs o 11 1144 1jd4 error 01109 tzb . 01 1144 11u4 error 01114 tzb . 02 1144 11m4 error 01119 tzb . 03 1144 11d4 error 01124 tzb . 04 1144 1/44 error 01129 tzb . 05 1144 1/u4 error 01134 tzb . 06 1144 1/m4 error 01139 tr 1 1174 7 01144 tra i 01 1174 11x4 error routine 01149 sel 2 0500 01154 wr r 1185 01159 tra i 03 1169 11f9 01164 tr 1 1174 01169 hlt j 0008 01174 tra i 02 1089 10q9 01179 tr 1 1194 7 2 002 01181 11 2 001 01182 | 2 002 01184 11 2 003 01187 008 2 001 01188 | 7 7 routine #009 7 use rcv-tzb to test for 7 ba8421 bits in mbr char 3. 7 01194 rcv u 1288 01199 tzb . 07 1209 1s+9 error 01204 tr 1 1239 error 01209 trs o 11 1249 1kd9 error 01214 tzb . 01 1249 12u9 error 01219 tzb . 02 1249 12m9 error 01224 tzb . 03 1249 12d9 error 01229 tzb . 04 1249 1s49 error 01234 tzb . 05 1249 1su9 error 01239 tzb . 06 1249 1sm9 error 01244 tr 1 1279 7 01249 tra i 01 1279 12x9 error routine 01254 sel 2 0500 01259 wr r 1290 01264 tra i 03 1274 12g4 01269 tr 1 1279 01274 hlt j 0007 01279 tra i 02 1194 11r4 01284 tr 1 1299 7 2 002 01287 111 2 001 01288 | 2 001 01289 1 2 003 01292 009 2 001 01293 | 7 7 routine #010 7 use rcv-tzb to test for 7 ba8421 bits in mbr char 4. 7 01299 rcv u 1394 01304 tzb . 07 1314 1ta4 error 01309 tr 1 1354 error 01314 trs o 11 1354 1le4 error 01319 tzb . 01 1354 13v4 error 01324 tzb . 02 1354 13n4 error 01329 tzb . 03 1354 13e4 error 01334 tzb . 04 1354 1t54 error 01339 tzb . 05 1354 1tv4 error 01344 tzb . 06 1354 1tn4 error 01349 tr 1 1384 7 01354 tra i 01 1384 13y4 error routine 01359 sel 2 0500 01364 wr r 1395 01369 tra i 03 1379 13g9 01374 tr 1 1384 01379 hlt j 0010 01384 tra i 02 1299 12r9 01389 tr 1 1404 7 2 004 01393 1111 2 001 01394 | 2 003 01397 010 2 001 01398 | 7 routine #011 7 execute sb 00 and sb 15 7 test 900. 7 01404 sb % 1460 01409 sb % 15 1460 1df0 01414 trs o 10 1424 1mk4 01419 tr 1 1454 7 01424 tra i 01 1454 14v4 error routine 01429 sel 2 0500 01434 wr r 1461 01439 tra i 03 1449 14d9 01444 tr 1 1454 01449 hlt j 0011 01454 tra i 02 1404 14-4 01459 tr 1 1469 7 2 004 01463 x011 2 001 01464 | 7 01469 rcv u 1530 routine #012 01474 sb % 02 1530 15l0 use sb to test mbr 1 bit to 01479 trs o 11 1494 1mi4 adder,rr and back to mbrjjj 01484 tzb . 01 1494 14z4 01489 tr 1 1524 7 01494 tra i 01 1524 15s4 01499 sel 2 0500 01504 wr r 1535 01509 tra i 03 1519 15a9 01514 tr 1 1524 01519 hlt j 0012 01524 tra i 02 1469 14o9 01529 tr 1 1544 7 7 2 005 01534 11111 2 003 01537 012 2 001 01538 | 7 01544 rcv u 1605 routine #013 01549 sb % 01 1605 16 5 use sb to test mbr 2 bit to 01554 trs o 11 1569 1nf9 adder,rr and back to mbr. 01559 tzb . 02 1569 15o9 01564 tr 1 1599 7 01569 tra i 01 1599 15z9 error routine 01574 sel 2 0500 01579 wr r 1610 01584 tra i 03 1594 15i4 01589 tr 1 1599 01594 hlt j 0013 01599 tra i 02 1544 15m4 01604 tr 1 1619 to next routine 7 2 005 01609 22222 2 003 01612 013 2 001 01613 | 7 01619 rcv u 1680 routine #014 01624 sb % 01 1680 16y0 use sb to test mbr 4 bit to 01629 trs o 11 1644 1od4 adder,rr and back to mbr 01634 tzb . 03 1644 16d4 01639 tr 1 1674 7 01644 tra i 01 1674 16x4 error routine 01649 sel 2 0500 01654 wr r 1685 01659 tra i 03 1669 16f9 01664 tr 1 1674 01669 hlt j 0014 01674 tra i 02 1619 16j9 01679 tr 1 1694 7 2 005 01684 44444 2 003 01687 014 2 001 01688 | 7 01694 rcv u 1755 routine #015 01699 sb % 01 1755 17v5 use sb to test mbr 8 bit to 01704 trs o 11 1719 1pa9 adder,rr and back to mbr. 01709 tzb . 04 1719 1x19 01714 tr 1 1749 7 01719 tra i 01 1749 17u9 01724 sel 2 0500 01729 wr r 1760 01734 tra i 03 1744 17d4 01739 tr 1 1749 01744 hlt j 0015 01749 tra i 02 1694 16r4 01754 tr 1 1769 7 7 2 005 01759 88888 2 003 01762 015 2 001 01763 | 7 01769 rcv u 1830 routine #016 01774 sb % 01 1830 18t0 use sb to test mbr 2 bit to 01779 trs o 11 1794 1pi4 adder,rr and back to mbr. 01784 tzb . 05 1794 1xz4 01789 tr 1 1824 7 01794 tra i 01 1824 18s4 error routine 01799 sel 2 0500 01804 wr r 1835 01809 tra i 03 1819 18a9 01814 tr 1 1824 01819 hlt j 0016 01824 tra i 02 1769 17o9 01829 tr 1 1844 to next routine 7 2 005 01834 2 003 01837 016 2 001 01838 | 7 01844 rcv u 1905 routine #017 01849 sb % 01 1905 19 5 use sb to test emit b bit to 01854 trs o 11 1869 1qf9 to rr and back to mbr. 01859 tzb . 06 1869 1yo9 01864 tr 1 1899 7 01869 tra i 01 1899 18z9 error routine 01874 sel 2 0500 01879 wr r 1910 01884 tra i 03 1894 18i4 01889 tr 1 1899 01894 hlt j 0017 01899 tra i 02 1844 18m4 01904 tr 1 1919 to next routine 7 2 005 01909 ----- 2 003 01912 017 2 001 01913 | 7 7 routine #018 7 use sb 01 to tes sup bit 7 to ad. then sb 09 to test 7 1 to ad routing. 7 01919 rcv u 2010 01924 sb % 01 2010 20/0 sup 1 bit to ad 01929 trs o 11 1964 1rf4 test 901 error 01934 tzb . 01 1944 19u4 01939 tr 1 1964 error 7 01944 sb % 09 2010 2-/0 1 to ad via dec carry in 01949 tzb . 01 1969 19w9 error 01954 trs o 11 1974 1rg4 error 01959 tr 1 2004 01964 sb % 09 2010 2-/0 error reset 01969 trs o 11 1974 1rg4 and tf 901 7 01974 tra i 01 2004 20 4 error routine 01979 sel 2 0500 01984 wr r 2015 01989 tra i 03 1999 19i9 01994 tr 1 2004 01999 hlt j 0018 02004 tra i 02 1919 19j9 02009 tr 1 2024 to next routine 7 2 005 02014 55555 2 003 02017 018 2 001 02018 | 7 7 7 routine #019 7 use sb02 to test sup 2 bit 7 to ad. then sb 10 to test 7 2 to ad routing. 7 02024 rcv u 2115 02029 sb % 02 2115 21j5 Sup 2 bit to ad 02034 trs o 11 2069 2-f9 test 901 error 02039 tzb . 02 2049 20m9 02044 tr 1 2069 error 7 02049 sb % 10 2115 2jj5 route 2 to ad 02054 tzb . 02 2074 20p4 error 02059 trs o 11 2079 2-g9 error 02064 tr 1 2109 02069 sb % 10 2115 2jj5 error reset 02074 trs o 11 2079 2-g9 and tf 901 7 02079 tra i 01 2109 21 9 error routine 02084 sel 2 0500 02089 wr r 2120 02094 tra i 03 2104 21+4 02099 tr 1 2109 02104 hlt j 0019 02109 tra i 02 2024 20k4 02114 tr 1 2129 7 7 2 005 02119 00000 2 003 02122 019 2 001 02123 | 7 7 7 routine #020 7 use sb 03 to test sup 4 bit 7 to ad. then sb 11 to test 7 4 to ad routing. 7 02129 rcv u 2220 02134 sb % 03 2220 22b0 Sup 4 bit to ad 02139 trs o 11 2174 2jg4 test 901 error 02144 tzb . 03 2154 21e4 02149 tr 1 2174 error 7 02154 sb % 11 2220 2kb0 route 4 to ad 02159 tzb . 03 2179 21g9 error 02164 trs o 11 2184 2jh4 error 02169 tr 1 2214 02174 sb % 11 2220 2kb0 error reset 02179 trs o 11 2184 2jh4 and tf 901 7 02184 tra i 01 2214 22/4 error routine 02189 sel 2 0500 02194 wr r 2225 02199 tra i 03 2209 22+9 02204 tr 1 2214 02209 hlt j 0020 02214 tra i 02 2129 21k9 02219 tr 1 2234 7 7 2 005 02224 66666 2 003 02227 020 2 001 02228 | 7 7 7 routine #021 7 use sb04 to test sup 8 bit 7 to ad. then sb 12 to test 7 8 to ad routing. 7 02234 rcv u 2325 02239 sb % 04 2325 2t25 Sup 8 bit to ad 02244 trs o 11 2279 2kg9 test 901 error 02249 tzb . 04 2259 2s59 02254 tr 1 2279 error 7 02259 sb % 12 2325 2c25 route 8 to ad 02264 tzb . 04 2284 2s84 error 02269 trs o 11 2289 2kh9 error 02274 tr 1 2319 02279 sb % 12 2325 2c25 error reset 02284 trs o 11 2289 2kh9 and tf 901 7 02289 tra i 01 2319 23/9 error routine 02294 sel 2 0500 02299 wr r 2330 02304 tra i 03 2314 23a4 02309 tr 1 2319 02314 hlt j 0021 02319 tra i 02 2234 22l4 02324 tr 1 2339 7 7 2 005 02329 99999 2 003 02332 021 2 001 02333 | 7 7 7 routine #022 7 use sb 03 to test sup 4 bit 7 to ad. then sb 11 to test 7 4 to ad routing. 7 02339 rcv u 2410 02344 sb % 09 2410 2m/0 SB 09 on = 02349 trs o 11 2374 2lg4 Error 02354 tzb . 01 2374 23x4 Error 02359 tzb . 02 2374 23p4 Error 02364 tzb . 04 2374 2t74 Error 02369 tzb . 03 2404 24+4 7 02374 tra i 01 2404 24 4 error routine 02379 sel 2 0500 02384 wr r 2415 02389 tra i 03 2399 23i9 02394 tr 1 2404 02399 hlt j 0022 02404 tra i 02 2339 23l9 7 02409 tr 1 2424 to next routine 7 7 2 005 02414 ===== 2 003 02417 022 2 001 02418 | 7 7 routine #023 7 use sb to test mbr char. 0 7 for picking or dropping bits. 7 02424 rcv u 2525 02429 sb % 09 2525 2ns5 mbr char 0 equal 7 02434 tzb . 01 2489 24y9 Error 02439 tzb . 02 2489 24q9 Error 02444 tzb . 03 2489 24h9 Error 02449 tzb . 04 2459 2u59 02454 tr 1 2489 error 02459 tzb . 05 2469 2uw9 02464 tr 1 2489 error 02469 tzb . 06 2479 2up9 02474 tr 1 2489 error 02479 trs o 11 2489 2mh9 test 901 02484 tr 1 2519 7 02489 tra i 01 2519 25/9 error routine 02494 sel 2 0500 02499 wr r 2530 02504 tra i 03 2514 25a4 02509 tr 1 2519 02514 hlt j 0023 02519 tra i 02 2424 24k4 02524 tr 1 2539 7 2 005 02529 7hhhh 2 003 02532 023 2 001 02533 | 7 7 routine #024 7 use sb to test mbr char. 0 7 for picking or dropping bits. 7 02539 rcv u 2640 02544 sb % 12 2640 2f40 mbr char 0 equal h 02549 tzb . 04 2604 2w04 Error 02554 tzb . 05 2604 2w 4 Error 02559 tzb . 06 2604 2w-4 Error 02564 tzb . 01 2574 25x4 02569 tr 1 2604 error 02574 tzb . 02 2584 25q4 02579 tr 1 2604 error 02584 tzb . 03 2594 25i4 02589 tr 1 2604 error 02594 trs o 11 2604 2o+4 test 901 02599 tr 1 2634 7 02604 tra i 01 2634 26t4 error routine 02609 sel 2 0500 02614 wr r 2645 02619 tra i 03 2629 26b9 02624 tr 1 2634 02629 hlt j 0024 02634 tra i 02 2539 25l9 02639 tr 1 2654 to next routine 7 2 005 02644 h7777 2 003 02647 024 2 001 02648 | 7 7 routine #025 7 use sb to test mbr char 1 7 for picking or dropping bits. 7 02654 rcv u 2756 02659 sb % 09 2756 2pv6 mbr char. 1 equal 7 02664 tzb . 01 2719 27/9 Error 02669 tzb . 02 2719 27j9 Error 02674 tzb . 03 2719 27a9 Error 02679 tzb . 04 2689 2w89 02684 tr 1 2719 error 02689 tzb . 05 2699 2wz9 02694 tr 1 2719 error 02699 tzb . 06 2709 2x-9 02704 tr 1 2719 error 02709 trs o 11 2719 2pa9 test 901 02714 tr 1 2749 7 02719 tra i 01 2749 27u9 error routine 02724 sel 2 0500 02729 wr r 2760 02734 tra i 03 2744 27d4 02739 tr 1 2749 02744 hlt j 0025 02749 tra i 02 2654 26n4 02754 tr 1 2769 to next routine 7 2 005 02759 h7hhh 2 003 02762 025 2 001 02763 | 7 7 routine #026 7 use sb to test mbr char 1 7 for picking or dropping bits. 7 02769 rcv u 2871 02774 sb % 12 2871 2h71 mbr char 1 equal h 02779 tzb . 04 2834 2y34 Error 02784 tzb . 05 2834 2yt4 Error 02789 tzb . 06 2834 2yl4 Error 02794 tzb . 01 2804 28 4 02799 tr 1 2834 error 02804 tzb . 02 2814 28j4 02809 tr 1 2834 error 02814 tzb . 03 2824 28b4 02819 tr 1 2834 error 02824 trs o 11 2834 2qc4 test 901 02829 tr 1 2864 7 02834 tra i 01 2864 28w4 error routine 02839 sel 2 0500 02844 wr r 2875 02849 tra i 03 2859 28e9 02854 tr 1 2864 02859 hlt j 0026 02864 tra i 02 2769 27o9 02869 tr 1 2884 to next routine 7 2 005 02874 7h777 2 003 02877 026 2 001 02878 | 7 7 routine #027 7 use sb to test mbr char 2 7 for picking or dropping bits. 7 02884 rcv u 2987 02889 sb % 09 2987 2ry7 mbr char. 2 equal 7 02894 tzb . 01 2949 29u9 Error 02899 tzb . 02 2949 29m9 Error 02904 tzb . 03 2949 29d9 Error 02909 tzb . 04 2919 2z19 02914 tr 1 2949 error 02919 tzb . 05 2929 2zs9 02924 tr 1 2949 error 02929 tzb . 06 2939 2zl9 02934 tr 1 2949 error 02939 trs o 11 2949 2rd9 error 02944 tr 1 2979 7 02949 tra i 01 2979 29x9 error routine 02954 sel 2 0500 02959 wr r 2990 02964 tra i 03 2974 29g4 02969 tr 1 2979 02974 hlt j 0026 02979 tra i 02 2884 28q4 02984 tr 1 2999 to next routine 7 2 005 02989 hh7hh 2 003 02992 027 2 001 02993 | 7 7 routine #028 7 use sb to test mbr char 2 7 for picking or dropping bits. 7 02999 rcv u 3102 03004 sb % 12 3102 3a02 mbr char. 2 equal h 03009 tzb . 04 3064 3 64 Error 03014 tzb . 05 3064 3 w4 Error 03019 tzb . 06 3064 3 o4 Error 03024 tzb . 01 3034 30t4 03029 tr 1 3064 error 03034 tzb . 02 3044 30m4 03039 tr 1 3064 error 03044 tzb . 03 3054 30e4 03049 tr 1 3064 error 03054 trs o 11 3064 3-f4 error 03059 tr 1 3094 7 03064 tra i 01 3094 30z4 error routine 03069 sel 2 0500 03074 wr r 3105 03079 tra i 03 3089 30h9 03084 tr 1 3094 03089 hlt j 0028 03094 tra i 02 2999 29r9 03099 tr 1 3114 7 2 005 03104 77h77 2 003 03107 028 2 001 03108 | 7 7 routine #029 7 use sb to test mbr char 3 7 for picking or dropping bits. 7 03114 rcv u 3218 03119 sb % 09 3218 3k/8 mbr char. 3 equal 7 03124 tzb . 01 3179 31x9 Error 03129 tzb . 02 3179 31p9 Error 03134 tzb . 03 3179 31g9 Error 03139 tzb . 04 3149 3/49 03144 tr 1 3179 error 03149 tzb . 05 3159 3/v9 03154 tr 1 3179 error 03159 tzb . 06 3169 3/o9 03164 tr 1 3179 error 03169 trs o 11 3179 3jg9 error 03174 tr 1 3209 7 03179 tra i 01 3209 32 9 error routine 03184 sel 2 0500 03189 wr r 3220 03194 tra i 03 3204 32+4 03199 tr 1 3209 03204 hlt j 0029 03209 tra i 02 3114 31j4 03214 tr 1 3229 to next routine 7 2 005 03219 hhh7h 2 003 03222 029 2 001 03223 | 7 7 routine #030 7 use sb to test mbr char 3 7 for picking or dropping bits. 7 03229 rcv u 3333 03234 sb % 12 3333 3c33 mbr char. 3 equal h 03239 tzb . 04 3294 3s94 Error 03244 tzb . 05 3294 3sz4 Error 03249 tzb . 06 3294 3sr4 Error 03254 tzb . 01 3264 32w4 03259 tr 1 3294 error 03264 tzb . 02 3274 32p4 03269 tr 1 3294 error 03274 tzb . 03 3284 32h4 03279 tr 1 3294 error 03284 trs o 11 3294 3ki4 error 03289 tr 1 3324 7 03294 tra i 01 3324 33s4 error routine 03299 sel 2 0500 03304 wr r 3335 03309 tra i 03 3319 33a9 03314 tr 1 3324 03319 hlt j 0030 03324 tra i 02 3229 32k9 03329 tr 1 3344 to next routine 7 2 005 03334 777h7 2 003 03337 030 2 001 03338 | 7 7 routine #031 7 use sb to test mbr char 4 7 for picking or dropping bits. 7 03344 rcv u 3449 03349 sb % 09 3449 3mu9 mbr char. 3 equal 7 03354 tzb . 01 3409 34 9 Error 03359 tzb . 02 3409 34-9 Error 03364 tzb . 03 3409 34+9 Error 03369 tzb . 04 3379 3t79 03374 tr 1 3409 error 03379 tzb . 05 3389 3ty9 03384 tr 1 3409 error 03389 tzb . 06 3399 3tr9 03394 tr 1 3409 error 03399 trs o 11 3409 3m+9 error 03404 tr 1 3439 7 03409 tra i 01 3439 34t9 error routine 03414 sel 2 0500 03419 wr r 3450 03424 tra i 03 3434 34c4 03429 tr 1 3439 03434 hlt j 0031 03439 tra i 02 3344 33m4 03444 tr 1 3459 to next routine 7 2 005 03449 hhhh7 2 003 03452 031 2 001 03453 | 7 7 routine #032 7 use sb to test mbr char 4 7 for picking or dropping bits. 7 03459 rcv u 3564 03464 sb % 12 3564 3e64 mbr char. 4 equal h 03469 tzb . 04 3524 3v24 Error 03474 tzb . 05 3524 3vs4 Error 03479 tzb . 06 3524 3vk4 Error 03484 tzb . 01 3494 34z4 03489 tr 1 3524 error 03494 tzb . 02 3504 35-4 03499 tr 1 3524 error 03504 tzb . 03 3514 35a4 03509 tr 1 3524 error 03514 trs o 11 3524 3nb4 error 03519 tr 1 3554 7 03524 tra i 01 3554 35v4 error routine 03529 sel 2 0500 03534 wr r 3565 03539 tra i 03 3549 35d9 03544 tr 1 3554 03549 hlt j 0032 03554 tra i 02 3459 34n9 03559 tr 1 3574 to next routine 7 2 005 03564 7777h 2 003 03567 032 2 001 03568 | 7 7 routine #033 7 execute sgn,rad,trz and trp 7 test zero, plus and no 900 chk 7 03574 eem 3 14 0000 0+-0 03579 spc , 0000 03584 sgn t 3660 03589 rad h 3664 tn dzt, set sign plus 03594 trz n 3604 test zero 03599 tr 1 3624 03604 trp m 3614 test plus 03609 tr 1 3624 03614 trs o 10 3624 3ok4 test no 900 check 03619 tr 1 3654 7 03624 tra i 01 3654 36v4 error routine 03629 sel 2 0500 03634 wr r 3665 03639 tra i 03 3649 36d9 03644 tr 1 3654 03649 hlt j 0033 03654 tra i 02 3574 35p4 03659 tr 1 3674 7 7 2 005 03664 0 - 2 003 03667 033 2 001 03668 | 7 03674 rad h 3729 routine #034 03679 trz n 3689 rad plus 1 and test 03684 trp m 3719 turn off of dzt. 7 03689 tra i 01 3719 37/9 error routine 03694 sel 2 0500 03699 wr r 3730 03704 tra i 03 3714 37a4 03709 tr 1 3719 03714 hlt j 0034 03719 tra i 02 3674 36p4 03724 tr 1 3739 to next routine 7 7 2 005 03729 A 2 003 03732 034 2 001 03733 | 7 7 7 03739 rad h 3799 routine #035 03744 trz n 3759 rad minus 1, test not zero 03749 trp m 3759 and sign minus 03754 tr 1 3789 7 03759 tra i 01 3789 37y9 error routine 03764 sel 2 0500 03769 wr r 3800 03774 tra i 03 3784 37h4 03779 tr 1 3789 03784 hlt j 0035 03789 tra i 02 3739 37l9 03794 tr 1 3809 7 7 2 005 03799 j 2 003 03802 035 2 001 03803 | 7 03809 rsu q 3869 routine #036 03814 trs o 10 3829 3qk9 execute rsu minus 1 . test 03819 trz n 3829 no 900. not zero and sign plus 03824 trp m 3859 7 03829 tra i 01 3859 38v9 error routine 03834 sel 2 0500 03839 wr r 3870 03844 tra i 03 3854 38e4 03849 tr 1 3859 03854 hlt j 0036 03859 tra i 02 3809 38-9 03864 tr 1 3879 7 7 2 005 03869 j 2 003 03872 036 2 001 03873 | 7 03879 rad h 3939 routine #037 03884 add g 3939 execute add zero to zero. 03889 trs o 10 3899 3qr9 test for zero and no 900 check 03894 trz n 3929 7 03899 tra i 01 3929 39s9 error routine 03904 sel 2 0500 03909 wr r 3940 03914 tra i 03 3924 39b4 03919 tr 1 3929 03924 hlt j 0037 03929 tra i 02 3879 38p9 03934 tr 1 3949 to next routine 7 7 2 005 03939 + 2 003 03942 037 2 001 03943 | 7 7 routine #038 7 execute sub and check for 900 7 on sub. do compl. addition 03949 rad h 4014 03954 add g 4013 add plus 1 to plus 0. 03959 sub p 4013 sub plus 1 from plus 1. 03964 trs o 10 3974 3rp4 03969 trz n 4004 test zero 7 03974 tra i 01 4004 40 4 error routine 03979 sel 2 0500 03984 wr r 4015 03989 tra i 03 3999 39i9 03994 tr 1 4004 03999 hlt j 0038 04004 tra i 02 3949 39m9 04009 tr 1 4024 7 7 2 004 04013 a 2 001 04014 + 2 003 04017 038 2 001 04018 | 7 04024 rad h 4083 routine #039 04029 add g 4083 add plus 1 to plus 1. 04034 sub p 4084 sub plus 2 from plus 2. 04039 trz n 4074 7 04044 tra i 01 4074 40x4 error routine 04049 sel 2 0500 04054 wr r 4085 04059 tra i 03 4069 40f9 04064 tr 1 4074 04069 hlt j 0039 04074 tra i 02 4024 40k4 04079 tr 1 4094 to next routine 7 7 2 004 04083 a 2 001 04084 b 2 003 04087 039 2 001 04088 | 7 7 04094 rad h 4164 routine #040 04099 add g 4163 add minus 0 to minus 1 04104 sub p 4164 sub minus 1 from minus 1 04109 trp m 4119 test plus 04114 tr 1 4124 04119 trz n 4154 test zero 7 04124 tra i 01 4154 41v4 error routine 04129 sel 2 0500 04134 wr r 4165 04139 tra i 03 4149 41d9 04144 tr 1 4154 04149 hlt j 0040 04154 tra i 02 4094 40r4 04159 tr 1 4174 7 7 2 005 04164 -j 2 003 04167 040 2 001 04168 | 7 04174 rsu q 4234 routine #041 04179 sub p 4233 sub plus 0 from minus 1. 04184 add g 4234 add plus 1 to minus 1 04189 trz n 4224 7 04194 tra i 01 4224 42s4 error routine 04199 sel 2 0500 04204 wr r 4235 04209 tra i 03 4219 42a9 04214 tr 1 4224 04219 hlt j 0041 04224 tra i 02 4174 41p4 04229 tr 1 4244 7 7 2 005 04234 +a 2 003 04237 041 2 001 04238 | 7 7 04244 rsu q 4304 routine #042 04249 sub p 4303 sub minus 0 from plus 1 04254 add g 4304 add minus 1 to plus 1 04259 trz n 4294 7 04264 tra i 01 4294 42z4 error routine 04269 sel 2 0500 04274 wr r 4305 04279 tra i 03 4289 42h9 04284 tr 1 4294 04289 hlt j 0042 04294 tra i 02 4244 42m4 04299 tr 1 4314 to next routine 7 7 2 005 04304 -j 2 003 04307 042 2 001 04308 | 7 7 04314 rad h 4374 routine #043 04319 add g 4373 test digit adder with add 04324 sub p 4374 zero to plus 8 and then sub 04329 trz n 4364 plus 8 from plus 8 7 04334 tra i 01 4364 43w4 error routine 04339 sel 2 0500 04344 wr r 4375 04349 tra i 03 4359 43e9 04354 tr 1 4364 04359 hlt j 0043 04364 tra i 02 4314 43j4 04369 tr 1 4384 7 2 005 04374 +h 2 003 04377 043 2 001 04378 | 7 04384 rad h 4444 routine #044 04389 add g 4444 test digit adder with add 04394 sub p 4443 plus 4 to plus 4 and then sub 04399 trz n 4434 plus 8 from plus 8. 7 04404 tra i 01 4434 44t4 error routine 04409 sel 2 0500 04414 wr r 4445 04419 tra i 03 4429 44b9 04424 tr 1 4434 04429 hlt j 0044 04434 tra i 02 4384 43q4 04439 tr 1 4454 7 7 2 005 04444 hd 2 003 04447 044 2 001 04448 | 7 04454 rad h 4524 routine #045 04459 add g 4524 test digit adder with add 04464 add g 4524 plus 2 to plus 2. plus 2 to 04469 add g 4524 plus 4. plus 2 to plus 6. 04474 sub p 4523 then sub plus 8 from plus 8. 04479 trz n 4514 7 04484 tra i 01 4514 45/4 error routine 04489 sel 2 0500 04494 wr r 4525 04499 tra i 03 4509 45+9 04504 tr 1 4514 04509 hlt j 0045 04514 tra i 02 4454 44n4 04519 tr 1 4534 to next routine 7 2 005 04524 hb 2 003 04527 045 2 001 04528 | 7 7 7 routine #046 7 test digit adder with 7 add signs alike plus. 7 04534 rad h 4623 rad plus 1 04539 add g 4623 add 1 to 1 04544 add g 4623 add 1 to 2 04549 add g 4623 add 1 to 3 04554 add g 4623 add 1 to 4 04559 add g 4623 add 1 to 5 04564 add g 4623 add 1 to 6 04569 add g 4623 add 1 to 7 04574 sub p 4624 sub plus 8 from plus 8. 04579 trz n 4614 7 04584 tra i 01 4614 46/4 error routine 04589 sel 2 0500 04594 wr r 4625 04599 tra i 03 4609 46+9 04604 tr 1 4614 04609 hlt j 0046 04614 tra i 02 4534 45l4 04619 tr 1 4634 7 7 2 004 04623 a 2 001 04624 h 2 003 04627 046 2 001 04628 | 7 7 routine #047 7 test digit adder with add. 04634 rad h 4693 04639 add g 4693 add plus 3 to plus 3 04644 sub p 4694 sub plus 6 from plus 6 04649 trz n 4684 7 04654 tra i 01 4684 46y4 error routine 04659 sel 2 0500 04664 wr r 4695 04669 tra i 03 4679 46g9 04674 tr 1 4684 04679 hlt j 0047 04684 tra i 02 4634 46l4 04689 tr 1 4704 to next routine 7 7 2 004 04693 c 2 001 04694 f 2 003 04697 047 2 001 04698 | 7 7 04704 rad h 4769 routine #048 04709 SUB P 4768 test sub. on sub do complement 04714 trp m 4729 addition and set sign minus. 04719 add g 4769 04724 trz n 4759 7 04729 tra i 01 4759 47v9 error routine 04734 sel 2 0500 04739 wr r 4770 04744 tra i 03 4754 47e4 04749 tr 1 4759 04754 hlt j 0048 04759 tra i 02 4704 47-4 04764 tr 1 4779 7 7 2 005 04769 ba 2 003 04772 048 2 001 04773 | 7 7 04779 rad h 4839 routine #049 04784 sub p 4838 test type cycle 2 on first sub 04789 sub p 4839 then sub plus 1 from plus 1. 04794 trz n 4829 7 04799 tra i 01 4829 48s9 error routine 04804 sel 2 0500 04809 wr r 4840 04814 tra i 03 4824 48b4 04819 tr 1 4829 04824 hlt j 0049 04829 tra i 02 4779 47p9 04834 tr 1 4849 7 7 2 005 04839 +a 2 003 04842 049 2 001 04843 | 7 7 04849 rad h 4909 routine #050 04854 sub p 4907 test type cycle 2 on first sub 04859 sub p 4908 then sub plus 7 from plus 7. 04864 trz n 4899 7 04869 tra i 01 4899 48z9 error routine 04874 sel 2 0500 04879 wr r 4910 04884 tra i 03 4894 48i4 04889 tr 1 4899 04894 hlt j 0050 04899 tra i 02 4849 48m9 04904 tr 1 4919 7 7 2 005 04909 agh 2 003 04912 050 2 001 04913 | 7 7 7 routine #051 7 do add, sub to test dig adder 7 carry out and carry in. 04919 rad h 4979 04924 add g 4979 add plus 6 to plus 6 04929 sub p 4984 sub plus 12 from plus 12 04934 trz n 4969 7 04939 tra i 01 4969 49w9 error routine 04944 sel 2 0500 04949 wr r 4985 04954 tra i 03 4964 49f4 04959 tr 1 4969 04964 hlt j 0051 04969 tra i 02 4919 49j9 04974 tr 1 4994 7 7 2 005 04979 0f 2 005 04984 1b 2 003 04987 051 2 001 04988 | 7 7 routine #052 7 test add with storage 7 greater than memory 04994 rad h 5053 04999 add g 5054 add plus 1 to plus 10 05004 sub p 5059 sub plus 11 from plus 11. 05009 trz n 5044 7 05014 tra i 01 5044 50u4 error routine 05019 sel 2 0500 05024 wr r 5060 05029 tra i 03 5039 50c9 05034 tr 1 5044 05039 hlt j 0052 05044 tra i 02 4994 49r4 05049 tr 1 5069 7 7 2 004 05053 1+ 2 001 05054 a 2 005 05059 1a 2 003 05062 052 2 001 05063 | 7 7 routine #053 7 test sub with memory 7 greater than storage 7 do type cycle 2. 05069 rad h 5134 05074 rad h 5144 rad plus 2 05079 sub p 5139 sub plus 001 from plus 2 05084 sub p 5139 sub plus 001 from plus 001 05089 trz n 5124 7 05094 tra i 01 5124 51s4 error routine 05099 sel 2 0500 05104 wr r 5145 05109 tra i 03 5119 51a9 05114 tr 1 5124 05119 hlt j 0053 05124 tra i 02 5069 50o9 05129 tr 1 5154 7 7 2 005 05134 77g 2 005 05139 00a 2 005 05144 b 2 003 05147 053 2 001 05148 | 7 7 routine #054 7 do add, sun to test dig adder 7 carry and dec. correction. 05154 rad h 5214 05159 add g 5214 add plus 08 to plus 08 05164 sub p 5219 sub plus 16 from plus 16. 05169 trz n 5204 7 05174 tra i 01 5204 52 4 error routine 05179 sel 2 0500 05184 wr r 5220 05189 tra i 03 5199 51i9 05194 tr 1 5204 05199 hlt j 0054 05204 tra i 02 5154 51n4 05209 tr 1 5229 to next routine 7 7 2 005 05214 0h 2 005 05219 1f 2 003 05222 054 2 001 05223 | 7 7 7 routine #055 7 do add, sub to test dig adder 7 carry and dec. correction 7 05229 rad h 5288 05234 add g 5289 add plus 9 to plus 07 05239 sub p 5294 sub plus 16 from plus 16 05244 trz n 5279 7 05249 tra i 01 5279 52x9 error routine 05254 sel 2 0500 05259 wr r 5295 05264 tra i 03 5274 52g4 05269 tr 1 5279 05274 hlt j 0055 05279 tra i 02 5229 52k9 05284 tr 1 5304 7 7 2 004 05288 0g 2 001 05289 i 2 005 05294 1f 2 003 05297 055 2 001 05298 | 7 7 7 routine #056 7 do add, sub to test dig adder 7 carry and dec. correction. 7 05304 rad h 5369 05309 add g 5373 add plus 08 to plus 04 05314 sub p 5374 sub plus 6 from plus 12 05319 sub p 5374 sub plus 6 from plus 6 05324 trz n 5359 7 05329 tra i 01 5359 53v9 error routine 05334 sel 2 0500 05339 wr r 5375 05344 tra i 03 5354 53e4 05349 tr 1 5359 05354 hlt j 0056 05359 tra i 02 5304 53-4 05364 tr 1 5384 to next routine 7 7 2 005 05369 0d 2 004 05373 0h 2 001 05374 f 2 003 05377 056 2 001 05378 | 7 7 05384 rad h 01 5444 54u4 routine #057 05389 trz n 01 5399 53z9 do rad to test tn asu dzt 05394 tr 1 5404 05399 trp m 01 5434 54t4 7 05404 tra i 01 5434 54t4 error routine 05409 sel 2 0500 05414 wr r 5445 05419 tra i 03 5429 54b9 05424 tr 1 5434 05429 hlt j 0057 05434 tra i 02 5384 53q4 05439 tr 1 5454 7 7 2 005 05444 - 2 003 05447 057 2 001 05448 | 7 05454 rad h 01 5509 55 9 routine #058 05459 trz n 01 5469 54w9 do rad to test tf asu dzt 05464 trp m 01 5499 54z9 and tf asu sign. 7 05469 tra i 01 5499 54z9 05474 sel 2 0500 05479 wr r 5510 05484 tra i 03 5494 54i4 05489 tr 1 5499 05494 hlt j 0058 05499 tra i 02 5454 54n4 05504 tr 1 5519 7 7 2 005 05509 a 2 003 05512 058 2 001 05513 | 7 7 05519 rad h 01 5579 55x9 routine #059 05524 trz n 01 5539 55t9 do rad to test tf asu dzt 05529 trp m 01 5539 55t9 and tn asu sign 05534 tr 1 5569 7 05539 tra i 01 5569 55w9 error routine 05544 sel 2 0500 05549 wr r 5580 05554 tra i 03 5564 55f4 05559 tr 1 5569 05564 hlt j 0059 05569 tra i 02 5519 55j9 05574 tr 1 5589 to next routine 7 7 2 005 05579 j 2 003 05582 059 2 001 05583 | 7 7 7 routine #060 7 do sub to test tf asu dzt 7 and tn asu sign minus. 7 05589 rad h 01 5653 56v3 05594 sub p 01 5654 56v4 dzt off, sign on 05599 trz n 01 5614 56/4 05604 trp m 01 5614 56/4 05609 tr 1 5644 7 05614 tra i 01 5644 56u4 error routine 05619 sel 2 0500 05624 wr r 5655 05629 tra i 03 5639 56c9 05634 tr 1 5644 05639 hlt j 0060 05644 tra i 02 5589 55q9 05649 tr 1 5664 7 7 2 004 05653 a 2 001 05654 b 2 003 05657 060 2 001 05658 | 7 7 routine #061 7 do rad to test for false 7 or tf of dzt and sign 7 triggers. 7 05664 rad h 5779 acc dzt off, sign on 05669 rad h 01 5778 57x8 asu dzt on, sign off 05674 trz n 5739 05679 trp m 5739 05684 trz n 01 5694 56z4 05689 tr 1 5739 05694 trp m 01 5704 57 4 05699 tr 1 5739 7 05704 rad h 01 5779 57x9 asu dzt off, sign on. 05709 rad h 5778 acc dzt on, sign off. 05714 trz n 01 5739 57t9 05719 trp m 01 5739 57t9 05724 trz n 5734 05729 tr 1 5739 05734 trp m 5769 7 05739 tra i 01 5769 57w9 error routine 05744 sel 2 0500 05749 wr r 5780 05754 tra i 03 5764 57f4 05759 tr 1 5769 05764 hlt j 0061 05769 tra i 02 5664 56o4 05774 tr 1 5789 to next routine 7 2 005 05779 -j 2 003 05782 061 2 001 05783 | 7 7 7 routine #062 7 do rad and add to test for 7 false tn and tf of acc dzt 7 05789 rad h 5859 rad 500, to tf dzt 05794 trz n 5819 05799 add g 5856 add +0 to tf dzt 05804 trz n 5819 05809 rad h 5862 rad 000 to tn dzt 05814 trz n 5849 7 05819 tra i 01 5849 58u9 error routine 05824 sel 2 0500 05829 wr r 5863 05834 tra i 03 5844 58d4 05839 tr 1 5849 05844 hlt j 0062 05849 tra i 02 5789 57q9 05854 tr 1 5874 7 7 2 002 05856 + 2 003 05859 50+ 2 003 05862 00+ 2 003 05865 062 2 001 05866 | 7 7 routine #063 7 execute cmp and test for 900. 7 test not high and equal 7 05874 rad h 5948 05879 cmp 4 5949 cmp zero versus zero 05884 trh k 5909 05889 tre l 5899 05894 tr 1 5909 05899 trs o 10 5909 5r-9 05904 tr 1 5939 7 05909 tra i 01 5939 59t9 error routine 05914 sel 2 0500 05919 wr r 5950 05924 tra i 03 5934 59c4 05929 tr 1 5939 05934 hlt j 0063 05939 tra i 02 5874 58p4 05944 tr 1 5959 to next routine 7 2 004 05948 + 2 001 05949 0 2 003 05952 063 2 001 05953 | 7 7 7 routine #064 7 cmp 2 versus 1 and test high 7 05959 rad h 6018 05964 cmp 4 6019 turn on high 05969 tre l 5979 05974 trh k 6009 7 05979 tra i 01 6009 60 9 error routine 05984 sel 2 0500 05989 wr r 6020 05994 tra i 03 6004 60+4 05999 tr 1 6009 06004 hlt j 0064 06009 tra i 02 5959 59n9 06014 tr 1 6029 7 7 2 004 06018 b 2 001 06019 1 2 003 06022 064 2 001 06023 | 7 7 7 routine #065 7 cmp 1 versus a and test high 06029 rad h 6089 06034 cmp 4 6089 turn on high 06039 tre l 6049 06044 trh k 6079 7 06049 tra i 01 6079 60x9 error routine 06054 sel 2 0500 06059 wr r 6090 06064 tra i 03 6074 60g4 06069 tr 1 6079 06074 hlt j 0065 06079 tra i 02 6029 60k9 06084 tr 1 6099 to next routine 7 7 2 005 06089 a 2 003 06092 065 2 001 06093 | 7 7 routine #066 7 cmp 19 versus 20 and test lo. 7 06099 rad h 6164 06104 cmp 4 6169 on cmp, turn high on first 06109 trh k 6124 followed by turn on lo. 06114 tre l 6124 06119 tr 1 6154 7 06124 tra i 01 6154 61v4 error routine 06129 sel 2 0500 06134 wr r 6170 06139 tra i 03 6149 61d9 06144 tr 1 6154 06149 hlt j 0066 06154 tra i 02 6099 60r9 06159 tr 1 6179 7 7 2 005 06164 1i 2 005 06169 20 2 003 06172 066 2 001 06173 | 7 7 routine #067 7 execute set and test 900 7 test for dzt on and sign plus 7 06179 rsu q 6249 rsu to tf dzt and set sign - 06184 set b 0000 set. tn dzt and set sign plus 06189 trs o 10 6209 6k-9 06194 trz n 6204 06199 tr 1 6209 06204 trp m 6239 7 06209 tra i 01 6239 62t9 error routine 06214 sel 2 0500 06219 wr r 6250 06224 tra i 03 6234 62c4 06229 tr 1 6239 06234 hlt j 0067 06239 tra i 02 6179 61p9 06244 tr 1 6259 to next routine 7 7 2 005 06249 a 2 003 06252 067 2 001 06253 | 7 7 7 routine #068 7 test cmp for reset 7 high trigger in cycle 2. 7 06259 rad h 6338 06264 cmp 4 6339 first cmp turns on hi. 06269 trh k 6279 06274 tr 1 6299 06279 set b 0000 06284 cmp 4 6339 second cmp resets high 06289 trh k 6299 and ends op in cycle 2. 06294 tre l 6329 7 06299 tra i 01 6329 63s9 error routine 06304 sel 2 0500 06309 wr r 6340 06314 tra i 03 6324 63b4 06319 tr 1 6329 06324 hlt j 0068 06329 tra i 02 6259 62n9 06334 tr 1 6349 7 7 2 004 06338 a 2 001 06339 2 003 06342 068 2 001 06343 | 7 7 routine #069 7 test set left for emit 7 zeros when smt comes on. 7 06349 rad h 6414 06354 set b 0000 06359 set b 0002 result 00 to sbr 06364 cmp 4 6419 cmp 00 versus 00. 06369 tre l 6404 7 06374 tra i 01 6404 64 4 error routine 06379 sel 2 0500 06384 wr r 6420 06389 tra i 03 6399 63i9 06394 tr 1 6404 06399 hlt j 0069 06404 tra i 02 6349 63m9 06409 tr 1 6429 to next routine 7 7 2 005 06414 a 2 005 06419 00 2 003 06422 069 2 001 06423 | 7 7 routine #070 7 test set left across a one 7 for sbr to ad routing 7 and tf dzt, 7 06429 rad h 6493 06434 set b 0001 06439 cmp 4 6494 cmp versus 1 06444 trz n 6454 test dzt off 06449 tre l 6484 7 06454 tra i 01 6484 64y4 error routine 06459 sel 2 0500 06464 wr r 6495 06469 tra i 03 6479 64g9 06474 tr 1 6484 06479 hlt j 0070 06484 tra i 02 6429 64k9 06489 tr 1 6504 7 7 2 004 06493 a 2 001 06494 1 2 003 06497 070 2 001 06498 | 7 7 routine #071 7 test rad and set for 7 tn and tf dzt. 7 06504 rad h 6574 rad and tf dzt 06509 trz n 6534 06514 trp m 6524 06519 tr 1 6534 06524 set b 0002 set to tn dzt 06529 trz n 6564 7 06534 tra i 01 6564 65w4 error routine 06539 sel 2 0500 06544 wr r 6575 06549 tra i 03 6559 65e9 06554 tr 1 6564 06559 hlt j 0071 06564 tra i 02 6504 65-4 06569 tr 1 6584 to next routine 7 7 2 005 06574 10+ 2 003 06577 071 2 001 06578 | 7 7 7 routine #072 7 do set across ampersand 7 to test a and b bits through 7 zone adder. 7 06584 sgn t 6644 sgn to place ampersand 06589 set b 0001 06594 cmp 4 6643 06599 tre l 6634 7 06604 tra i 01 6634 66t4 error routine 06609 sel 2 0500 06614 wr r 6645 06619 tra i 03 6629 66b9 06624 tr 1 6634 06629 hlt j 0072 06634 tra i 02 6584 65q4 06639 tr 1 6704 7 7 2 005 06644 +0 2 003 06647 072 2 001 06648 | 7 7 7 routine #073 7 execute lod and test 900. 7 06704 set b 0000 06709 lod 8 6764 06714 trs o 10 6724 6pk4 06719 tr 1 6754 7 06724 tra i 01 6754 67v4 06729 sel 2 0500 06734 wr r 6765 06739 tra i 03 6749 67d9 06744 tr 1 6754 06749 hlt j 0073 06754 tra i 02 6704 67-4 06759 tr 1 6774 to next routine 7 7 2 005 06764 2 003 06767 073 2 001 06768 | 7 7 06774 rad h 6829 routine #074 06779 lod 8 6827 test lod for turn on dzt 06784 trz n 6819 7 06789 tra i 01 6819 68/9 error routine 06794 sel 2 0500 06799 wr r 6831 06804 tra i 03 6814 68a4 06809 tr 1 6819 06814 hlt j 0074 06819 tra i 02 6774 67p4 06824 tr 1 6839 7 7 2 005 06829 0 a 2 001 06830 0 2 003 06833 074 2 001 06834 | 7 7 06839 rad h 6899 routine #075 06844 trp m 6859 test lod for set sign plus 06849 lod 8 6899 06854 trp m 6889 7 06859 tra i 01 6889 68y9 error routine 06864 sel 2 0500 06869 wr r 6900 06874 tra i 03 6884 68h4 06879 tr 1 6889 06884 hlt j 0075 06889 tra i 02 6839 68l9 06894 tr 1 6909 7 7 2 005 06899 j 2 003 06902 075 2 001 06903 | 7 7 06909 set b 0000 routine #076 06914 set b 0001 test lod for turn off dzt 06919 lod 8 6974 06924 trz n 6934 06929 tr 1 6964 7 06934 tra i 01 6964 69w4 error routine 06939 sel 2 0500 06944 wr r 6975 06949 tra i 03 6959 69e9 06954 tr 1 6964 06959 hlt j 0076 06964 tra i 02 6909 69-9 06969 tr 1 6984 to next routine 7 7 2 005 06974 1 2 003 06977 076 2 001 06978 | 7 7 7 routine #077 7 test lod for turn off dzt 7 when mbr equals hypersand. 7 06984 set b 0000 06989 set b 0001 06994 lod 8 7049 06999 trz n 7009 07004 tr 1 7039 7 07009 tra i 01 7039 70t9 error routine 07014 sel 2 0500 07019 wr r 7050 07024 tra i 03 7034 70c4 07029 tr 1 7039 07034 hlt j 0077 07039 tra i 02 6984 69q4 07044 tr 1 7059 7 7 2 005 07049 - 2 003 07052 077 2 001 07053 | 7 7 routine #078 7 test lod instruction 7 07059 set b 0001 07064 lod 8 7119 lod a one 07069 cmp 4 7119 cmp versus one 07074 tre l 7109 7 07079 tra i 01 7109 71 9 error routine 07084 sel 2 0500 07089 wr r 7120 07094 tra i 03 7104 71+4 07099 tr 1 7109 07104 hlt j 0078 07109 tra i 02 7059 70n9 07114 tr 1 7129 7 7 2 005 07119 1 2 003 07122 078 2 001 07123 | 7 7 7 routine #079 7 test lod and cmp instructions 07129 set b 0002 07134 lod 8 7204 lod 12 07139 cmp 4 7209 cmp versus 11 07144 trh k 7154 07149 tr 1 7164 07154 cmp 4 7204 cmp versus 12 07159 tre l 7194 7 07164 tra i 01 7194 71z4 error routine 07169 sel 2 0500 07174 wr r 7210 07179 tra i 03 7189 71h9 07184 tr 1 7194 07189 hlt j 0079 07194 tra i 02 7129 71k9 07199 tr 1 7219 7 7 2 005 07204 12 2 005 07209 11 2 003 07212 079 2 001 07213 | 7 7 routine #080 7 use lod and cmp to 7 test the zone addr 7 07219 set b 0001 07224 lod 8 7288 lod a 07229 cmp 4 7289 cmp versus 1 07234 tre l 7249 07239 trh k 7249 07244 tr 1 7279 7 07249 tra i 01 7279 72x9 error routine 07254 sel 2 0500 07259 wr r 7290 07264 tra i 03 7274 72g4 07269 tr 1 7279 07274 hlt j 0080 07279 tra i 02 7219 72j9 07284 tr 1 7299 to next routine 7 7 2 004 07288 a 2 001 07289 1 2 003 07292 080 2 001 07293 | 7 7 7 routine #081 7 use lod and cmp to 7 test the zone adder 7 07299 set b 0001 07304 lod 8 7368 lod j 07309 cmp 4 7369 cmp versus 1 07314 tre l 7329 07319 trh k 7329 07324 tr 1 7359 7 07329 tra i 01 7359 73v9 error routine 07334 sel 2 0500 07339 wr r 7370 07344 tra i 03 7354 73e4 07349 tr 1 7359 07354 hlt j 0081 07359 tra i 02 7299 72r9 07364 tr 1 7379 7 7 2 004 07368 j 2 001 07369 1 2 003 07372 081 2 001 07373 | 7 7 7 routine #082 7 use lod and cmp to 7 test the zone adder 7 07379 set b 0001 07384 lod 8 7448 lod s 07389 cmp 4 7449 cmp versus 2 07394 tre l 7409 07399 trh k 7409 07404 tr 1 7439 7 07409 tra i 01 7439 74t9 error routine 07414 sel 2 0500 07419 wr r 7450 07424 tra i 03 7434 74c4 07429 tr 1 7439 07434 hlt j 0082 07439 tra i 02 7379 73p9 07444 tr 1 7459 to next routine 7 7 2 004 07448 s 2 001 07449 2 2 003 07452 082 2 001 07453 | 7 7 7 routine #083 7 use lod and cmp to 7 test the zone adder. 07459 set b 0001 07464 lod 8 7528 lod b 07469 cmp 4 7529 cmp versus s 07474 tre l 7489 07479 trh k 7489 07484 tr 1 7519 7 07489 tra i 01 7519 75/9 error routine 07494 sel 2 0500 07499 wr r 7530 07504 tra i 03 7514 75a4 07509 tr 1 7519 07514 hlt j 0083 07519 tra i 02 7459 74n9 07524 tr 1 7539 7 7 2 004 07528 b 2 001 07529 s 2 003 07532 083 2 001 07533 | 7 7 7 routine #084 7 use lod and cmp to 7 test the zone adder. 7 07539 set b 0001 07544 lod 8 7608 lod a 07549 cmp 4 7609 cmp versus j 07554 tre l 7569 07559 trh k 7569 07564 tr 1 7599 7 07569 tra i 01 7599 75z9 error routine 07574 sel 2 0500 07579 wr r 7610 07584 tra i 03 7594 75i4 07589 tr 1 7599 07594 hlt j 0084 07599 tra i 02 7539 75l9 07604 tr 1 7619 to next routine 7 7 2 004 07608 a 2 001 07609 j 2 003 07612 084 2 001 07613 | 7 7 7 routine #085 7 use lod and cmp to 7 test the zone adder 7 07619 set b 0001 07624 lod 8 7683 lod j 07629 cmp 4 7684 cmp versus a 07634 tre l 7644 07639 trh k 7674 7 07644 tra i 01 7674 76x4 error routine 07649 sel 2 0500 07654 wr r 7685 07659 tra i 03 7669 76f9 07664 tr 1 7674 07669 hlt j 0085 07674 tra i 02 7619 76j9 07679 tr 1 7694 7 7 2 004 07683 j 2 001 07684 a 2 003 07687 085 2 001 07688 | 7 7 7 routine #086 7 use lod and cmp to 7 test the zone adder 7 07694 set b 0001 07699 lod 8 7758 lod s 07704 cmp 4 7759 cmp versus k 07709 tre l 7719 07714 trh k 7749 7 07719 tra i 01 7749 77u9 error routine 07724 sel 2 0500 07729 wr r 7760 07734 tra i 03 7744 77d4 07739 tr 1 7749 07744 hlt j 0086 07749 tra i 02 7694 76r4 07754 tr 1 7769 to next routine 7 7 2 004 07758 s 2 001 07759 k 2 003 07762 086 2 001 07763 | 7 7 7 routine #087 7 use lod and cmp to 7 test the zone adder. 7 07769 set b 0001 07774 lod 8 7833 lod s 07779 cmp 4 7834 cmp versus b 07784 tre l 7794 07789 trh k 7824 7 07794 tra i 01 7824 78s4 error routine 07799 sel 2 0500 07804 wr r 7835 07809 tra i 03 7819 78a9 07814 tr 1 7824 07819 hlt j 0087 07824 tra i 02 7769 77o9 07829 tr 1 7844 7 7 2 004 07833 s 2 001 07834 b 2 003 07837 087 2 001 07838 | 7 7 7 routine #088 7 test cmp instruction and 7 mbr,sbr recognition. 7 07844 set b 0001 07849 lod 8 7909 lod ampersand 07854 cmp 4 7908 cmp versus blank 07859 tre l 7869 07864 trh k 7899 7 07869 tra i 01 7899 78z9 error routine 07874 sel 2 0500 07879 wr r 7910 07884 tra i 03 7894 78i4 07889 tr 1 7899 07894 hlt j 0088 07899 tra i 02 7844 78m4 07904 tr 1 7919 to next routine 7 7 2 005 07909 + 2 003 07912 088 2 001 07913 | 7 7 7 routine #089 7 test cmp instruction and 7 mbr,sbr recognition. 7 7 07919 set b 0001 07924 lod 8 7983 load ampersand 07929 cmp 4 7984 cmp versus lozenge 07934 tre l 7944 07939 trh k 7974 7 7 07944 tra i 01 7974 79x4 error routine 07949 sel 2 0500 07954 wr r 7985 07959 tra i 03 7969 79f9 07964 tr 1 7974 07969 hlt j 0089 07974 tra i 02 7919 79j9 07979 tr 1 7994 2 2 2 004 07983 + 2 001 07984 | 2 003 07987 089 2 001 07988 | 7 7 7 routine #090 7 test cmp instruction and 7 mbr,sbr recognition. 7 7 07994 set b 0001 07999 lod 8 8058 lod l 08004 cmp 4 8059 cmp versus $ 08009 tre l 8019 08014 trh k 8049 7 08019 tra i 01 8049 80u9 error routine 08024 sel 2 0500 08029 wr r 8060 08034 tra i 03 8044 80d4 08039 tr 1 8049 08044 hlt j 0090 08049 tra i 02 7994 79r4 08054 tr 1 8069 to next routine 7 7 2 004 08058 l 2 001 08059 $ 2 003 08062 090 2 001 08063 | 7 7 7 routine #091 7 test cmp instruction and 7 mbr,sbr recognition. 7 08069 set b 0001 08074 lod 8 8138 lod blank 08079 cmp 4 8139 cmp versus ampersand 08084 trh k 8099 08089 tre l 8099 08094 tr 1 8129 7 08099 tra i 01 8129 81s9 error routine 08104 sel 2 0500 08109 wr r 8140 08114 tra i 03 8124 81b4 08119 tr 1 8129 08124 hlt j 0091 08129 tra i 02 8069 80o9 08134 tr 1 8149 7 7 2 005 08139 + 2 003 08142 091 2 001 08143 | 7 7 7 routine #092 7 test cmp instruction and 7 mbr,sbr recognition. 7 08149 set b 0001 08154 lod 8 8218 lod lozenge 08159 cmp 4 8219 cmp versus ampersand 08164 trh k 8179 08169 tre l 8179 08174 tr 1 8209 7 08179 tra i 01 8209 82 9 error routine 08184 sel 2 0500 08189 wr r 8220 08194 tra i 03 8204 82+4 08199 tr 1 8209 08204 hlt j 0092 08209 tra i 02 8149 81m9 08214 tr 1 8229 to next routine 7 7 2 004 08218 ( 2 001 08219 + 2 003 08222 092 2 001 08223 | 7 7 7 routine #093 7 test cmp instruction and 7 mbr,sbr recognition 7 08229 set b 0001 08234 lod 8 8298 lod % 08239 cmp 4 8299 cmp versus u 08244 tre l 8259 08249 trh k 8259 08254 tr 1 8289 7 08259 tra i 01 8289 82y9 error routine 08264 sel 2 0500 08269 wr r 8300 08274 tra i 03 8284 82h4 08279 tr 1 8289 08284 hlt j 0093 08289 tra i 02 8229 82k9 08294 tr 1 8309 7 7 2 004 08298 % 2 001 08299 u 2 003 08302 093 2 001 08303 | 7 7 7 routine #094 7 test cmp instruction and 7 mbr,sbr recognition. 7 08309 set b 0001 08314 lod 8 8369 lod / 08319 cmp 4 8369 cmp versus / 08324 tre l 8359 7 08329 tra i 01 8359 83v9 error routine 08334 sel 2 0500 08339 wr r 8370 08344 tra i 03 8354 83e4 08349 tr 1 8359 08354 hlt j 0094 08359 tra i 02 8309 83-9 08364 tr 1 8379 to next routine 7 7 2 005 08369 / 2 003 08372 094 2 001 08373 | 7 7 7 routine #095 7 test cmp instruction and 7 mbr,sbr recognition. 7 08379 set b 0001 08384 lod 8 8439 lod blank 08389 cmp 4 8439 cmp versus blank 08394 tre l 8429 7 08399 tra i 01 8429 84s9 error routine 08404 sel 2 0500 08409 wr r 8440 08414 tra i 03 8424 84b4 08419 tr 1 8429 08424 hlt j 0095 08429 tra i 02 8379 83p9 08434 tr 1 8449 7 7 2 005 08439 2 003 08442 095 2 001 08443 | 7 7 7 routine #096 7 test cmp instruction and 7 mbr,sbr recognition. 7 08449 set b 0001 08454 lod 8 8509 lod * 08459 cmp 4 8509 cmp versus * 08464 tre l 8499 7 08469 tra i 01 8499 84z9 error routine 08474 sel 2 0500 08479 wr r 8510 08484 tra i 03 8494 84i4 08489 tr 1 8499 08494 hlt j 0096 08499 tra i 02 8449 84m9 08504 tr 1 8519 to next routine 7 7 2 005 08509 * 2 003 08512 096 2 001 08513 | 7 7 7 routine #097 7 execute unl and test 900. 7 08519 set b 0000 08524 unl 7 8579 08529 trs o 10 8539 8nl9 08534 tr 1 8569 7 08539 tra i 01 8569 85w9 error routine 08544 sel 2 0500 08549 wr r 8580 08554 tra i 03 8564 85f4 08559 tr 1 8569 08564 hlt j 0097 08569 tra i 02 8519 85j9 08574 tr 1 8589 7 7 2 005 08579 2 003 08582 097 2 001 08583 | 7 7 routine #098 7 test unl instructon for 7 route digit adder out. 7 08589 set b 0001 08594 lod 8 8672 lod 3 08599 unl 7 8673 unl 3 08604 cmp 4 8673 08609 tre l 8619 08614 tr 1 8634 7 08619 lod 8 8674 reset unl field to blank 08624 unl 7 8673 if routine is good. 08629 tr 1 8664 7 08634 tra i 01 8664 86w4 error routine 08639 sel 2 0500 08644 wr r 8675 08649 tra i 03 8659 86e9 08654 tr 1 8664 08659 hlt j 0098 08664 tra i 02 8589 85q9 08669 tr 1 8684 to next routine 7 7 2 003 08672 3 2 001 08673 2 001 08674 2 003 08677 098 2 001 08678 | 7 7 7 routine #099 7 test unl instruction for 7 route zone adder out. 7 08684 set b 0001 08689 lod 8 8767 lod ampersand 08694 unl 7 8768 unl ampersand 08699 cmp 4 8768 08704 tre l 8714 08709 tr 1 8729 7 08714 lod 8 8769 reset unl field to blank 08719 unl 7 8768 if routine is good. 08724 tr 1 8759 7 08729 tra i 01 8759 87v9 error routine 08734 sel 2 0500 08739 wr r 8770 08744 tra i 03 8754 87e4 08749 tr 1 8759 08754 hlt j 0099 08759 tra i 02 8684 86q4 08764 tr 1 8779 7 7 2 003 08767 + 2 001 08768 2 001 08769 2 003 08772 099 2 001 08773 | 7 08779 set b 0001 routine #100 08784 lod 8 8862 test unl instruction for 08789 unl 7 8863 suppress adder carry. 08794 cmp 4 8863 08799 tre l 8809 08804 tr 1 8824 7 08809 lod 8 8864 reset unl field to blank 08814 unl 7 8863 if routine is good 08819 tr 1 8854 7 08824 tra i 01 8854 88v4 error routine 08829 sel 2 0500 08834 wr r 8865 08839 tra i 03 8849 88d9 08844 tr 1 8854 08849 hlt j 0100 08854 tra i 02 8779 87p9 08859 tr 1 8874 to next routine 7 7 2 003 08862 | 2 001 08863 2 001 08864 2 003 08867 100 2 001 08868 | 7 7 7 routine #101 7 test unl routine 7 08874 set b 0002 08879 lod 8 8964 lod pz 08884 unl 7 8969 unl pz 08889 set b 0003 08894 cmp 4 8969 08899 tre l 8909 08904 tr 1 8924 7 08909 lod 8 8974 reset unl field 08914 unl 7 8969 if routine is good 08919 tr 1 8954 7 08924 tra i 01 8954 89v4 error routine 08929 sel 2 0500 08934 wr r 8975 08939 tra i 03 8949 89d9 08944 tr 1 8954 08949 hlt j 0101 08954 tra i 02 8874 88p4 08959 tr 1 8984 to next routine 7 7 2 005 08964 pz 2 005 08969 0 2 005 08974 0 2 003 08977 101 2 001 08978 | 7 7 7 routine #102 7 test transfer store location 7 store ic value of 6669 7 08984 set b 0000 08989 set b 0005 08994 unl 7 9094 clear rcv area 08999 lod 8 9029 09004 unl 7 6664 place tsl inst at 6664 09009 lod 8 9034 09014 unl 7 6669 place tr inst at 6669 09019 rcv u 9091 09024 tr 1 6664 transfer to 6664 to do tsl 7 09029 tr 1 01 9039 90t9 09034 tr 1 9054 7 09039 lod 8 9099 09044 cmp 4 9094 cmp stored ic value 09049 tre l 9084 7 09054 tra i 01 9084 90y4 error routine 09059 sel 2 0500 09064 wr r 9100 09069 tra i 03 9079 90g9 09074 tr 1 9084 09079 hlt j 0102 09084 tra i 02 8984 89q4 09089 tr 1 9109 to next routine 7 7 2 005 09094 00000 rcv area 2 005 09099 06669 correct ic value stored 2 003 09102 102 2 001 09103 | 7 7 7 routine #103 7 test transfer store location 7 store ic value of 9984 7 09109 set b 0000 09114 set b 0004 09119 unl 7 9224 clear rcv area 09124 set b 0005 09129 lod 8 9159 09134 unl 7 19979 z979 place tsl inst. at 199979 09139 lod 8 9164 09144 unl 7 19984 z984 place tr inst. at 19984 09149 rcv u 9221 09154 tr 1 19979 z979 transfer to 19979 to do tsl 7 09159 tr 1 01 9169 91w9 09164 tr 1 9184 7 09169 lod 8 9229 09174 cmp 4 9224 cmp stored ic value 09179 tre l 9214 7 09184 tra i 01 9214 92/4 error routine 09189 sel 2 0500 09194 wr r 9230 09199 tra i 03 9209 92+9 09204 tr 1 9214 09209 hlt j 0103 09214 tra i 02 9109 91-9 09219 tr 1 9239 to next routine 7 7 2 005 09224 -0000 rcv area 2 005 09229 -z984 correct ic value storesd 2 003 09232 103 2 001 09233 | 7 7 7 routine #104 7 test transfer store location. 7 store ic 159694 in 7080 mode. 7 09239 eem 3 14 0000 0+-0 09244 set b 0000 09249 set b 0004 09254 unl 7 9369 clear rcv area 09259 set b 0005 09264 lod 8 9294 09269 unl 7 159689 i68i place tsl inst. at 159689 09274 lod 8 9299 09279 unl 7 159694 i69d place tr inst. at 159694 09284 rcv u 9366 09289 tr 1 159689 i68i transfer to 159689 to do tsl 7 09294 tr 1 01 9304 93 4 09299 tr 1 9319 7 09304 lod 8 9374 09309 cmp 4 9369 cmp ic value stored 09314 tre l 9349 7 09319 tra i 01 9349 93u9 error routine 09324 sel 2 0500 09329 wr r 9375 09334 tra i 03 9344 93d4 09339 tr 1 9349 09344 hlt j 0104 09349 tra i 02 9239 92l9 7 09354 rcv u 0306 first use of error 09359 tr 1 01 0204 02 4 sub-routine 09364 tr 1 9384 to next routine 7 7 2 005 09369 -0000 rcv area 2 005 09374 -i69d correct ic value stored 2 003 09377 104 2 001 09378 | 7 7 7 routine #105 7 use lod to test look ahead 7 during mem rd mode. 7 09384 eem 3 14 0000 0+-0 09389 spc , 0000 09394 set b 0000 09399 set b 0004 09404 lod 8 9491 lod 3456 from char. 1/6 09409 spc , 0002 09414 cmp 4 9489 cmp 34 09419 tre l 9429 09424 tr 1 9449 09429 set b 0000 09434 spc , 0000 09439 cmp 4 9491 cmp 56 09444 tre l 9479 7 09449 tra i 01 9479 94x9 error routine 09454 sel 2 0500 09459 wr r 9495 09464 tra i 03 9474 94g4 09469 tr 1 9479 09474 hlt j 0105 09479 tra i 02 9384 93q4 09484 tr 1 9504 7 7 2 010 09494 0123456789 2 003 09497 105 2 001 09498 | 7 7 routine #106 7 use lod to test mem rd 7 mode on initial address 0/5. 09504 eem 3 14 0000 0+-0 09509 spc , 0000 09514 set b 0000 09519 set b 0005 09524 lod 8 9580 lod 12345 from char. 0/5 09529 cmp 4 9589 09534 tre l 9569 7 09539 tra i 01 9569 95w9 error routine 09544 sel 2 0500 09549 wr r 9590 09554 tra i 03 9564 95f4 09559 tr 1 9569 09564 hlt j 0106 09569 tra i 02 9504 95-4 09574 tr 1 9599 to next routine 7 7 2 010 09584 0123456789 2 005 09589 12345 2 003 09592 106 2 001 09593 | 7 7 7 routine #107 7 use unl to test mem 7 rd-wr mode for tn mrt 7 09599 eem 3 14 0000 0+-0 09604 spc , 0000 09609 set b 0000 09614 set b 0005 09619 unl 7 9694 clear unl 09624 unl 7 9689 area 09629 lod 8 9699 09634 unl 7 9691 unl 23456 to char. 1/6 09639 cmp 4 9691 09644 tre l 9679 7 09649 tra i 01 9679 96x9 error routine 09654 sel 2 0500 09659 wr r 9674 09664 tra i 03 9674 96g4 09669 tr 1 9679 09674 hlt j 0107 09679 tra i 02 9599 95r9 09684 tr 1 9709 7 7 2 010 09694 0000000000 2 005 09699 23456 2 003 09702 107 2 001 09703 | 7 7 7 routine #108 7 use unl to test mem rd-wr 7 mode with initial address 0/5. 7 09709 eem 3 14 0000 0+-0 09714 spc , 0000 09719 set b 0000 09724 set b 0005 09729 unl 7 9804 clear unl area 09734 unl 7 9799 09739 lod 8 9809 09744 unl 7 9800 unl 12345 to char. 0/5 09749 cmp 4 9800 09754 tre l 9789 7 09759 tra i 01 9789 97y9 error routine 09764 sel 2 0500 09769 wr r 9810 09774 tra i 03 9784 97h4 09779 tr 1 9789 09784 hlt j 0108 09789 tra i 02 9709 97-9 09794 tr 1 9819 to next routine 7 7 2 010 09804 0000000000 2 005 09809 12345 2 003 09812 108 2 001 09813 | 7 7 7 routine #109 7 use lod and cmp to test 7 look ahead in stor rd and 7 stor r-w modes. 7 09819 eem 3 14 0000 0+-0 09824 spc , 0006 09829 set b 0000 09834 set b 0004 09839 lod 8 9894 lod 4 digits in sbr char 6. 09844 cmp 4 9894 cmp 4 digits 09849 tre l 9884 7 09854 tra i 01 9884 98y4 error routine 09859 sel 2 0500 09864 wr r 9895 09869 tra i 03 9879 98g9 09874 tr 1 9884 09879 hlt j 0109 09884 tra i 02 9819 98j9 09889 tr 1 9904 7 7 7 2 005 09894 -1076 2 003 09897 109 2 001 09898 | 7 7 7 routine #110 7 use lod and cmp to test 7 storage modes on initial 7 address of char 7. 7 09904 eem 3 14 0000 0+-0 09909 spc , 0007 09914 set b 0000 09919 set b 0004 09924 lod 8 9979 lod 4 digits in sbr char 7. 09929 cmp 4 9979 cmp 4 digits 09934 tre l 9969 7 09939 tra i 01 9969 99w9 error routine 09944 sel 2 0500 09949 wr r 9980 09954 tra i 03 9964 99f4 09959 tr 1 9969 09964 hlt j 0110 09969 tra i 02 9904 99-4 09974 tr 1 10034 034 to next routine 7 7 2 005 09979 -2107 2 003 09982 110 2 001 09983 | 7 7 7 routine #111 7 use lod and cmp to test 7 look ahead in memory and 7 storage modes. 7 10034 eem 3 14 0000 0+-0 10039 spc , 0005 10044 set b 0000 10049 set b 0005 clear storage field 7 10054 spc , 0006 10059 lod 8 10162 162 lod 4 digits from mem. char. 2 10064 cmp 4 10162 162 into sbr char. 6 and compare. 10069 tre l 10079 079 10074 tr 1 10119 119 7 10079 lod 8 10161 161 10084 cmp 4 10161 161 lod 4 digits from mem. char. 1 10089 tre l 10099 099 into sbr char. 6 and compare. 10094 tr 1 10119 119 7 10099 spc , 0005 10104 lod 8 10161 161 lod 5 digits from mem. char 1 10109 cmp 4 10161 161 into sbr char. 5 and compare 10114 tre l 10149 149 7 10119 tra i 01 10149 1u9 error routine 10124 sel 2 0500 10129 wr r 10163 163 10134 tra i 03 10144 1d4 10139 tr 1 10149 149 10144 hlt j 0111 10149 tra i 02 10034 0l4 10154 tr 1 10174 174 to next routine 7 7 2 008 10162 --789012 2 003 10165 111 2 001 10166 | 7 7 7 routine #112 7 use lod and cmp to test 7 memory and storage modes. 7 on initial address of 0/5 7 in mem and char. 7 in sbr 7 10174 eem 3 14 0000 0+-0 10179 spc , 0006 10184 set b 0000 10189 set b 0004 clear storage field 7 10194 lod 8 10295 295 10199 cmp 4 10295 295 lod 4 digits from mem. char 0 10204 tre l 10214 214 into sbr char 6 and compare 10209 tr 1 10254 254 7 10214 spc , 0007 10219 lod 8 10295 295 lod 3 digits from mem. char 0 10224 cmp 4 10295 295 into sbr char 7 and compare. 10229 tre l 10239 239 10234 tr 1 10254 254 7 10239 lod 8 10296 296 lod 3 digits from mem. char 1 10244 cmp 4 10296 296 into sbr char 7 and compare 10249 tre l 10284 284 7 10254 tra i 01 10284 2y4 error routine 10259 sel 2 0500 10264 wr r 10297 297 10269 tra i 03 10279 2g9 10274 tr 1 10284 284 10279 hlt j 0112 10284 tra i 02 10174 1p4 10289 tr 1 10309 309 to next routine 7 7 2 007 10296 78901 2 003 10299 112 2 001 10300 | 7 7 7 routine #113 7 use unl and cmp to test 7 look ahead in memory 7 and storage modes. 7 10309 eem 3 14 0000 0+-0 10314 spc , 0000 10319 set b 0000 10324 set b 0006 10329 unl 7 10452 452 clear memory field 10334 spc , 0005 10339 set b 0005 10344 lod 8 10459 459 lod 10765 in sbr char 5 7 10349 unl 7 10451 451 unl 5 digits from sbr char. 5 10354 cmp 4 10451 451 to mem char 1 and compare 10359 tre l 10369 369 10364 tr 1 10409 409 7 10369 spc , 0006 10374 unl 7 10451 451 unl 4 digits from sbr char. 6 10379 cmp 4 10451 451 to mem char 1 and compare 10384 tre l 10394 394 10389 tr 1 10409 409 7 10394 unl 7 10452 452 unl 4 digits from sbr char. 6 10399 cmp 4 10452 452 to mem char 2 and compare 10404 tre l 10439 439 7 10409 tra i 01 10439 4t9 error routine 10414 sel 2 0500 10419 wr r 10460 460 10424 tra i 03 10434 4c4 10429 tr 1 10439 439 10434 hlt j 0113 10439 tra i 02 10309 3-9 10444 tr 1 10469 469 to next routine 7 7 2 008 10452 --000000 mem field 2 002 10454 2 005 10459 10765 stor. field 2 003 10462 113 2 001 10463 | 7 7 7 routine #114 7 use unl and cmp to test 7 memory and storage modes 7 on initial addresses of 0/5 7 in mem and char. 7 in sbr 7 10469 eem 3 14 0000 0+-0 10474 spc , 0000 10479 set b 0000 10484 set b 0004 10489 unl 7 10621 621 clear memory field 10494 spc , 0006 10499 set b 0003 10504 lod 8 10624 624 lod 076 in sbr char 6 7 10509 unl 7 10620 620 unl 3 digits from sbr char. 6 10514 cmp 4 10620 620 to mem char. 0 and compare 10519 tre l 10529 529 10524 tr 1 10569 569 7 10529 spc , 0007 10534 unl 7 10620 620 unl 2 digits from sbr char. 7 10539 cmp 4 10620 620 to mem char. 0 and compare 10544 tre l 10554 554 10549 tr 1 10569 569 7 10554 unl 7 10621 621 10559 cmp 4 10621 621 10564 tre l 10599 599 7 10569 tra i 01 10599 5z9 error routine 10574 sel 2 0500 10579 wr r 10625 625 10584 tra i 03 10594 5i4 10589 tr 1 10599 599 10594 hlt j 0114 10599 tra i 02 10469 4o9 10604 rcv u 0306 10609 tr 1 01 0204 02 4 10614 tr 1 10634 634 to next routine 7 7 2 007 10621 ---0000 2 003 10624 076 2 003 10627 114 2 001 10628 | 7 7 7 routine #115 7 use lod and cmp to test 7 all char. of sbr for bit 7 picks or drops. 7 10634 eem 3 14 0000 0+-0 10639 spc , 0000 10644 set b 0000 10649 set b 0010 clear storage 10654 lod 8 10714 714 lod 10 characters 10659 cmp 4 10714 714 and compare 10664 tre l 10699 699 7 10669 tra i 01 10699 6z9 error routine 10674 sel 2 0500 10679 wr r 10715 715 10684 tra i 03 10694 6i4 10689 tr 1 10699 699 10694 hlt j 0115 10699 tra i 02 10634 6l4 10704 tr 1 10724 724 7 7 2 010 10714 70h70h70h7 2 003 10717 115 2 001 10718 | 7 7 ROUTine #116 7 use lod and cmp to test 7 all char. of sbr for bit 7 picks or drops. 7 10724 eem 3 14 0000 0+-0 10729 spc , 0000 10734 set b 0000 10739 set b 0010 clear storage 10744 lod 8 10804 804 lod 10 characters 10749 cmp 4 10804 804 and compare them 10754 tre l 10789 789 7 10759 tra i 01 10789 7y9 error routine 10764 sel 2 0500 10769 wr r 10805 805 10774 tra i 03 10784 7h4 10779 tr 1 10789 789 10784 hlt j 0116 10789 tra i 02 10724 7k4 10794 tr 1 10814 814 to next routine 7 2 010 10804 h70h70h70h 2 003 10807 116 2 001 10808 | 7 7 7 routine #117 7 use lod and cmp to test 7 all char. of sbr for bit 7 picks of drops. 7 10814 eem 3 14 0000 0+-0 10819 spc , 0000 10824 set b 0000 10829 set b 0010 clear storage 10834 lod 8 10894 894 lod 10 characters 10839 cmp 4 10894 894 and compare them. 10844 tre l 10879 879 7 10849 tra i 01 10879 8x9 error routine 10854 sel 2 0500 10859 wr r 10895 895 10864 tra i 03 10874 8g4 10869 tr 1 10879 879 10874 hlt j 0117 10879 tra i 02 10814 8j4 10884 tr 1 10904 904 7 7 2 010 10894 0h70h70h70 2 003 10897 117 2 001 10898 | 7 7 7 routine #118 7 use unl to test for bit 7 pick or drop in the alu to 7 mem switch. 7 10904 eem 3 14 0000 0+-0 10909 spc , 0004 10914 set b 0000 10919 set b 0009 10924 unl 7 10994 994 clear mem field 10929 lod 8 11004 /004 10934 unl 7 10994 994 unl 9 test characters 10939 cmp 4 10994 994 10944 tre l 10979 979 7 10949 tra i 01 10979 9x9 error routine 10954 sel 2 0500 10959 wr r 11005 /005 10964 tra i 03 10974 9g4 10969 tr 1 10979 979 10974 hlt j 0118 10979 tra i 02 10904 9-4 10984 tr 1 11014 /014 to next routine 7 7 2 010 10994 -000000000 mem field 2 010 11004 -0h70h70h7 test field 2 003 11007 118 2 001 11008 | 7 7 7 routine #119 7 use unl to test for bit 7 pick or drop in the 7 alu to mem. switch 7 11014 eem 3 14 0000 0+-0 11019 spc , 0004 11024 set b 0000 11029 set b 0009 11034 unl 7 11104 /104 clear mem. field 11039 lod 8 11114 /114 11044 unl 7 11104 /104 unl 9 test characters 11049 cmp 4 11104 /104 11054 tre l 11089 /089 7 11059 tra i 01 11089 /0y9 error routine 11064 sel 2 0500 11069 wr r 11115 /115 11074 tra i 03 11084 /0h4 11079 tr 1 11089 /089 11084 hlt j 0119 11089 tra i 02 11014 /0j4 11094 tr 1 11124 /124 7 7 2 010 11104 -000000000 mem field 2 010 11114 -70h70h70h test field 2 003 11117 119 2 001 11118 | 7 7 routine #120 7 use unl to test for bit 7 pick of drop in the 7 alu to mem. switch. 7 11124 eem 3 14 0000 0+-0 11129 spc , 0004 11134 set b 0000 11139 set b 0009 11144 unl 7 11224 /224 clear mem. field 11149 lod 8 11234 /234 11154 unl 7 11224 /224 unl 9 test characters. 11159 cmp 4 11224 /224 11164 tre l 11199 /199 7 11169 tra i 01 11199 /1z9 error routine 11174 sel 2 0500 11179 wr r 11235 /235 11184 tra i 03 11194 /1i4 11189 tr 1 11199 /199 11194 hlt j 0120 11199 tra i 02 11124 /1k4 11204 rcv u 0306 11209 tr 1 01 0204 02 4 11214 tr 1 11244 /244 to next routine 7 7 2 010 11224 -000000000 mem field 2 010 11234 -h70h70h70 2 003 11237 120 2 001 11238 | 7 7 routine #121 7 execute shr and test for 7 no 900 chk and dzt on. 7 11244 eem 3 14 0000 0+-0 11249 spc , 0000 11254 set b 0000 11259 shr c 0000 11264 trs o 10 11274 /kp4 11269 trz n 11304 /304 7 11274 tra i 01 11304 /3 4 error routine 11279 sel 2 0500 11284 wr r 11310 /310 11289 tra i 03 11299 /2i9 11294 tr 1 11304 /304 11299 hlt j 0121 11304 tra i 02 11244 /2m4 11309 tr 1 11319 /319 7 7 7 2 003 11312 121 2 001 11313 | 7 11319 rsu q 11381 /381 routine #122 11324 shr c 0000 test shr for tf dzt and leave 11329 trz n 11344 /344 sign minus in type cycle 2. 11334 trp m 11344 /344 11339 tr 1 11374 /374 7 11344 tra i 01 11374 /3x4 error routine 11349 sel 2 0500 11354 wr r 11382 /382 11359 tra i 03 11369 /3f9 11364 tr 1 11374 /374 11369 hlt j 0122 11374 tra i 02 11319 /3j9 11379 tr 1 11394 /394 next routine 7 7 2 002 11381 + 1 2 003 11384 122 2 001 11385 | 7 7 7 routine #123 7 test shr. repeat type cycle 1 7 and set sign plus 7 in type cycle 2. 7 7 11394 rsu q 11456 /456 11399 shr c 0001 11404 trz n 11414 /414 11409 tr 1 11419 /419 11414 trp m 11449 /449 7 11419 tra i 01 11449 /4u9 error routine 11424 sel 2 0500 11429 wr r 11457 /457 11434 tra i 03 11444 /4d4 11439 tr 1 11449 /449 11444 hlt j 0123 11449 tra i 02 11394 /3r4 11454 tr 1 11469 /469 7 2 002 11456 + 1 2 003 11459 123 2 001 11460 | 7 7 routine #124 7 test shr. repeat type 7 cycle 2 and set sign plus. 7 11469 rsu q 11533 /533 11474 shr c 0001 11479 trz n 11489 /489 11484 tr 1 11494 /494 11489 trp m 11524 /524 7 11494 tra i 01 11524 /5s4 error routine 11499 sel 2 0500 11504 wr r 11534 /534 11509 tra i 03 11519 /5a9 11514 tr 1 11524 /524 11519 hlt j 0124 11524 tra i 02 11469 /4o9 11529 tr 1 11544 /544 next routine 7 7 2 004 11533 + 001 2 003 11536 124 2 001 11537 | 7 7 7 routine #125 7 test shr. repeat type 7 cycle 2 and turn off dzt. 7 11544 rsu q 11613 /613 11549 shr c 0001 11554 trz n 11574 /574 11559 trp m 11574 /574 11564 cmp 4 11615 /615 11569 tre l 11604 /604 7 11574 tra i 01 11604 /6 4 error routine 11579 sel 2 0500 11584 wr r 11616 /616 11589 tra i 03 11599 /5i9 11594 tr 1 11604 /604 11599 hlt j 0125 11604 tra i 02 11544 /5m4 11609 tr 1 11624 /624 7 7 2 004 11613 + 101 2 002 11615 10 2 003 11618 125 2 001 11619 | 7 7 7 routine #126 7 execute lng and test 7 for no 900 check 7 11624 rad h 11686 /686 11629 lng d 0000 11634 trs o 10 11649 /om9 11639 cmp 4 11687 /687 11644 tre l 11679 /679 7 11649 tra i 01 11679 /6x9 error routine 11654 sel 2 0500 11659 wr r 11688 /688 11664 tra i 03 11674 /6g4 11669 tr 1 11679 /679 11674 hlt j 0126 11679 tra i 02 11624 /6k4 11684 tr 1 11699 /699 next routine 7 7 2 002 11686 + 1 2 001 11687 1 2 003 11690 126 2 001 11691 | 7 7 7 routine #127 7 test lng for step mac 1, 7 sac 7 11699 rad h 11756 /756 11704 lng d 0001 11709 cmp 4 11758 /758 11714 tre l 11749 /749 7 11719 tra i 01 11749 /7u9 next routine 11724 sel 2 0500 11729 wr r 11759 /759 11734 tra i 03 11744 /7d4 11739 tr 1 11749 /749 11744 hlt j 0127 11749 tra i 02 11699 /6r9 11754 tr 1 11769 /769 7 7 2 002 11756 + 1 2 002 11758 10 2 003 11761 127 2 001 11762 | 7 7 7 routine #128 7 test lng for emit zero 7 to storage. 7 11769 rad h 11832 /832 11774 shr c 0001 11779 lng d 0001 11784 cmp 4 11834 /834 11789 tre l 11824 /824 7 11794 tra i 01 11824 /8s4 error routine 11799 sel 2 0500 11804 wr r 11835 /835 11809 tra i 03 11819 /8a9 11814 tr 1 11824 /824 11819 hlt j 0128 11824 tra i 02 11769 /7o9 11829 tr 1 11844 /844 next routine 7 7 2 003 11832 + 12 2 002 11834 10 2 003 11837 128 2 001 11838 | 7 7 7 routine #129 7 test lng for repeat type 7 cycle 2 on sacc not 1, 2, 4. 7 check stor. mark generation. 11844 eem 3 14 0000 0+-0 11849 spc , 0010 11854 rad h 11917 /917 11859 lng d 0002 11864 spc , 0005 locate stor. mark 11869 set b 0003 set left across stor. mark 11874 trz n 11909 /909 7 11879 tra i 01 11909 /9 9 error routine 11884 sel 2 0500 11889 wr r 11918 /918 11894 tra i 03 11904 /9+4 11899 tr 1 11909 /909 11904 hlt j 0129 11909 tra i 02 11844 /8m4 11914 tr 1 11929 /929 7 7 2 003 11917 x1a 2 003 11920 129 2 001 11921 | 7 7 11929 eem 3 14 0000 0+-0 routine #130 11934 spc , 0000 test spc 1, 2 and 4 triggers 11939 set b 0007 11944 spc , 0007 set spc to char 7 11949 cmp 4 11988 /988 cmp stor mark vs gm 11954 tre l 11989 /989 7 11959 tra i 01 11989 /9y9 error routine 11964 sel 2 0500 11969 wr r 11995 /995 11974 tra i 03 11984 /9h4 11979 tr 1 11989 /989 11984 hlt j 0130 11989 tra i 02 11929 /9k9 11994 tr 1 12004 s004 to next routine 7 7 2 003 11997 130 2 001 11998 | 7 7 12004 eem 3 14 0000 0+-0 routine #131 12009 spc , 0000 test spc 8 and 16 triggers 12014 set b 0024 12019 spc , 0030 spc to word 3 char. zero 12024 cmp 4 12073 s073 cmp stor. mark vs gm 12029 tre l 12064 s064 should be equal. 7 12034 tra i 01 12064 s0w4 error routine 12039 sel 2 0500 12044 wr r 12070 s070 12049 tra i 03 12059 s0e9 12054 tr 1 12064 s064 12059 hlt j 0131 12064 tra i 02 12004 s0-4 12069 tr 1 12079 s079 7 7 2 003 12072 131 2 001 12073 | 7 7 12079 eem 3 14 0000 0+-0 routine #132 12084 spc , 0000 test spc 32, 64, 128 triggers 12089 lng d 0032 12094 set b 0001 lng to step 32, 64, 128 on. 12099 lod 8 12158 s158 lod group mark. spc to 0700 12104 spc , 0700 and cmp the group mark 12109 cmp 4 12158 s158 12114 tre l 12149 s149 7 12119 tra i 01 12149 s1u9 error routine 12124 sel 2 0500 12129 wr r 12155 s155 12134 tra i 03 12144 s1d4 12139 tr 1 12149 s149 12144 hlt j 0132 12149 tra i 02 12079 s0p9 12154 tr 1 12164 s164 to next routine 7 7 2 003 12157 132 2 001 12158 | 7 7 7 routine #133 7 use shr to test step 7 sac and spc plus 1. 7 12164 eem 3 14 0000 0+-0 12169 SPC , 0000 12174 set b 0255 12179 lod 8 12510 s510 lod 255 non-zero characters. 12184 shr c 0255 shr to step sac and spc to 12189 trz n 12199 s199 storage mark position. 12194 tr 1 12219 s219 12199 rad h 12513 s513 rad and step all sac off 12204 shr c 0001 shr and step all spc off 12209 cmp 4 12512 s512 12214 tre l 12249 s249 7 12219 tra i 01 12249 s2u9 error routine 12224 sel 2 0500 12229 wr r 12514 s514 12234 tra i 03 12244 s2d4 12239 tr 1 12249 s249 12244 hlt j 0133 12249 tra i 02 12164 s1o4 12254 tr 1 12524 s524 7 7 2 001 12255 255 char. field for rout. #133 and #134 2 031 12286 6666666555555554444444433333333 2 032 12318 2222222211111111zzzzzzzzyyyyyyyy 2 032 12350 xxxxxxxxwwwwwwwwvvvvvvvvuuuuuuuu 2 032 12382 ttttttttssssssssrrrrrrrrqqqqqqqq 2 032 12414 ppppppppoooooooonnnnnnnnmmmmmmmm 2 032 12446 llllllllkkkkkkkkjjjjjjjjiiiiiiii 2 032 12478 hhhhhhhhggggggggffffffffeeeeeeee 2 032 12510 ddddddddccccccccbbbbbbbbaaaaaaaa 2 003 12513 x9i 2 003 12516 133 2 001 12517 | 7 routine #134 7 use lng to test step 7 sac and spc minus 2 7 12524 eem 3 14 0000 0+-0 12529 spc , 0000 12534 set b 0255 12539 lod 8 12510 s510 lod 255 non-zero characters 12544 lng d 0254 lng to step counters 12549 shr c 0000 shr to test single non-zero 12554 trz n 12574 s574 character left in storage 12559 lng d 0001 lng to step one more 12564 shr c 0000 12569 trz n 12604 s604 7 12574 tra i 01 12604 s6 4 error routine 12579 sel 2 0500 12584 wr r 12610 s610 12589 tra i 03 12599 s5i9 12594 tr 1 12604 s604 12599 hlt j 0134 12604 tra i 02 12524 s5k4 12609 tr 1 12619 s619 to next routine 7 7 2 003 12612 134 2 001 12613 | 7 7 routine #135 7 use rad and spc to test 7 set sac to ssr routine 7 for asu 01 to asu 08. 7 12619 eem 3 14 0000 0+-0 12624 set b 01 0000 00 0 12629 set b 01 0256 02v6 clear bank 1 to zeros 12634 rad h 01 12876 s8x6 1 into asu 01 12639 rad h 02 12877 s8p7 2 into asu 02 12644 rad h 03 12878 s8g8 3 into asu 03 12649 rad h 04 12879 sy79 4 into asu 04 12654 rad h 05 12880 syy0 5 into asu 05 12659 rad h 06 12881 syq1 6 into asu 06 12664 rad h 07 12882 syh2 7 into asu 07 12669 rad h 08 12883 sq83 8 into asu 08 7 12674 spc , 1000 12679 cmp 4 12885 s885 test asu 01 12684 tre l 12694 s694 12689 tr 1 12834 s834 12694 spc , 1020 12699 cmp 4 12886 s886 test asu 02 12704 tre l 12714 s714 12709 tr 1 12834 s834 12714 spc , 1100 12719 cmp 4 12887 s887 test asu 03 12724 tre l 12734 s734 12729 tr 1 12834 s834 12734 spc , 1120 12739 cmp 4 12888 s888 test asu 04 12744 tre l 12754 s754 12749 tr 1 12834 s834 12754 spc , 1200 12759 cmp 4 12889 s889 test asu 05 12764 tre l 12774 s774 12769 tr 1 12834 s834 12774 spc , 1220 12779 cmp 4 12890 s890 test asu 06 12784 tre l 12794 s794 12789 tr 1 12834 s834 12794 spc , 1300 12799 cmp 4 12891 s891 test asu 07 12804 tre l 12814 s814 12809 tr 1 12834 s834 12814 spc , 1320 12819 cmp 4 12892 s892 test asu 08 12824 spc , 0000 12829 tre l 12869 s869 7 12834 spc , 0000 error routine 12839 tra i 01 12869 s8w9 12844 sel 2 0500 12849 wr r 12893 s893 12854 tra i 03 12864 s8f4 12859 tr 1 12869 s869 12864 hlt j 0135 12869 tra i 02 12619 s6j9 12874 tr 1 12904 s904 to next routine 7 7 2 009 12883 -abcdefgh 2 009 12892 -12345678 2 003 12895 135 2 001 12896 | 7 7 7 routine #136 7 use rad and spc to test 7 set sax to ssr routings 7 for asu 09 to asu 15 12904 eem 3 14 0000 0+-0 12909 set b 09 0000 0- 0 12914 set b 09 0256 0kv6 clear bank 1 to zeros 12919 rad h 09 13137 tjt7 9 into asu 1 12924 rad h 10 13139 tjl9 10 into asu 10 12929 rad h 11 13141 tjd1 11 into asu 11 12934 rad h 12 13143 ta43 12 into asu 12 12939 rad h 13 13145 tau5 13 into asu 13 12944 rad h 14 13147 tam7 14 into asu 14 12949 rad h 15 13149 tad9 15 into asu 15 7 12954 spc , 1400 12959 cmp 4 13152 t152 test asu 09 12964 tre l 12974 s974 12969 tr 1 13094 t094 12974 spc , 1420 12979 cmp 4 13154 t154 test asu 10 12984 tre l 12994 s994 12989 tr 1 13094 t094 12994 spc , 1500 12999 cmp 4 13156 t156 test asu 11 13004 tre l 13014 t014 13009 tr 1 13094 t094 13014 spc , 1520 13019 cmp 4 13158 t158 test asu 12 13024 tre l 13034 t034 13029 tr 1 13094 t094 13034 spc , 1600 13039 cmp 4 13160 t160 test asu 13 13044 tre l 13054 t054 13049 tr 1 13094 t094 13054 spc , 1620 13059 cmp 4 13162 t162 test asu 14 13064 tre l 13074 t074 13069 tr 1 13094 t094 13074 spc , 1700 13079 cmp 4 13164 t164 test asu 15 13084 spc , 0000 13089 tre l 13129 t129 7 13094 spc , 0000 error routine 13099 tra i 01 13129 t1s9 13104 sel 2 0500 13109 wr r 13165 t165 13114 tra i 03 13124 t1b4 13119 tr 1 13129 t129 13124 hlt j 0135 13129 tra i 02 12904 s9-4 13134 tr 1 13554 t554 to next routine 7 2 015 13149 -0i1+1a1b1c1d1e 2 015 13164 -09101112131415 2 003 13167 136 2 001 13168 | 7 7 7 routine #150 7 test set bit 05 and 13. 7 13554 set b 0001 13559 lod 8 13650 t650 13564 unl 7 13652 t652 reset test char. to x 7 13569 sb % 05 13652 twv2 change x to 7 13574 set b 01 0001 00 1 13579 lod 8 01 13651 t6v1 13584 cmp 4 01 13652 t6v2 test 7 13589 tre l 13599 t599 13594 tr 1 13614 t614 7 13599 sb % 13 13652 tfv2 change 7 to x 13604 cmp 4 13652 t652 test x 13609 tre l 13644 t644 7 13614 tra i 01 13644 t6u4 error routine 13619 sel 2 0500 13624 wr r 13653 t653 13629 tra i 03 13639 t6c9 13634 tr 1 13644 t644 13639 hlt j 0150 13644 tra i 02 13554 t5n4 13649 tr 1 13664 t664 to next routine 7 7 2 002 13651 x7 2 001 13652 x test char. 2 003 13655 150 2 001 13656 | 7 7 7 routine #151 7 test sb 07 for reverse a 7 13664 set bv 0001 13669 lod 8 13760 t760 13674 unl 7 13762 t762 reset test char. to z 7 13679 sb % 07 13762 txf2 change z to 9 13684 set b 01 0001 00 1 13689 lod 8 01 13761 t7w1 13694 cmp 4 01 13762 t7w2 test 9 13699 tre l 13709 t709 13704 tr 1 13724 t724 7 13709 sb % 07 13762 txf2 change 9 to z 13714 cmp 4 13762 t762 test z 13719 tre l 13754 t754 7 13724 tra i 01 13754 t7v4 error routine 13729 sel 2 0500 13734 wr r 13763 t763 13739 tra i 03 13749 t7d9 13744 tr 1 13754 t754 13749 hlt j 0151 13754 tra i 02 13664 t6o4 13759 tr 1 13774 t774 to next routine 7 7 2 002 13761 z9 2 001 13762 z test char. 2 003 13765 151 2 001 13766 | 7 7 7 routine #152 7 test sb 06 and 14. 7 13774 set b 0001 13779 lod 8 13880 t880 13784 unl 7 13882 t882 rest test char. to n 7 13789 sb % 06 13882 tyq2 change n to 5 13794 set b 01 0001 00 1 13799 lod 8 01 13881 t8y1 13804 cmp 4 01 13882 t8y2 test 5 13809 tre l 13819 t819 13814 tr 1 13834 t834 7 13819 sb % 14 13882 thq2 change 5 to n 13824 cmp 4 13882 t882 test 5 13829 tre l 13864 t864 7 13834 tra i 01 13864 t8w4 error routine 13839 sel 2 0500 13844 wr r 13883 t883 13849 tra i 03 13859 t8e9 13854 tr 1 13864 t864 13859 hlt j 0152 13864 tra i 02 13774 t7p4 13869 rcv u 0306 13874 tr 1 01 0204 02 4 13879 tr 1 13894 t894 to next routine 7 7 2 002 13881 n5 2 001 13882 n test char. 2 003 13885 152 2 001 13886 | 7 7 7 routine #153 7 test indirect addressing 7 in 705-3 mode 7 13894 lem 3 15 0000 0++0 13899 sb % 13 13909 ti 9 place a bit for i/a 13904 set b 0001 13909 lod 8 13914 t914 lod group mark indirectly 13914 nop a 13968 t968 13919 cmp 4 13968 t968 13924 tre l 13959 t959 7 13929 tra i 01 13959 t9v9 error routine 13934 sel 2 0500 13939 wr r 13965 t965 13944 tra i 03 13954 t9e4 13949 tr 1 13959 t959 13954 hlt j 0153 13959 tra i 02 13894 t8r4 13964 tr 1 13974 t974 7 7 2 003 13967 153 2 001 13968 | 7 7 routine #154 7 test indirect addressing 7 in 7080 mode using eia. 7 13974 eem 3 14 0000 0+-0 13979 set b 0001 13984 eia , 10 0000 0--0 lod group mark indirectly 13989 lod 8 13994 t994 13994 nop a 14048 u048 13999 cmp 4 14048 u048 14004 tre l 14039 u039 7 14009 tra i 01 14039 u0t9 error routine 14014 sel 2 0500 14019 wr r 14045 u045 14024 tra i 03 14034 u0c4 14029 tr 1 14039 u039 14034 hlt j 0154 14039 tra i 02 13974 t9p4 14044 tr 1 14054 u054 to next routine 7 7 2 003 14047 154 2 001 14048 | 7 7 7 routine #155 7 execute store a blank and 7 test for no 900 check. 7 14054 set b 0000 14059 st f 14126 u126 on store, result a blank 14064 trs o 10 14089 u-q9 back to memory. 14069 set b 0001 14074 lod 8 14125 u125 14079 cmp 4 14126 u126 14084 tre l 14119 u119 7 14089 tra i 01 14119 u1/9 error routine 14094 sel 2 0500 14099 wr r 14127 u127 14104 tra i 03 14114 u1a4 14109 tr 1 14119 u119 14114 hlt j 0155 14119 tra i 02 14054 u0n4 14124 tr 1 14139 u139 7 7 2 001 14125 2 001 14126 2 003 14129 155 2 001 14130 | 7 7 7 routine #156 7 test store for smt on to route 7 dig ad out, emit a. emit b. 7 14139 set b 0001 14144 lod 8 14220 u220 14149 unl 7 14222 u222 reset store field 7 14154 set b 0000 14159 st f 14222 u222 result plus zero to memory 14164 set b 0001 14169 lod 8 14221 u221 14174 cmp 4 14222 u222 14179 tre l 14214 u214 7 14184 tra i 01 14214 u2/4 error routine 14189 sel 2 0500 14194 wr r 14223 u223 14199 tra i 03 14209 u2+9 14204 tr 1 14214 u214 14209 hlt j 0156 14214 tra i 02 14139 u1l9 14219 tr 1 14234 u234 to next routine 7 7 2 001 14220 0 2 001 14221 +0 2 001 14222 0 2 003 14225 156 2 001 14226 | 7 7 7 routine #157 7 test store instruction 7 store a minus one. 7 14234 set b 0000 14239 set b 0002 14244 unl 7 14308 u308 reset store field 14249 rsu q 14306 u306 rsu minus 1 14254 st f 14308 u308 emit b bit in cycle 3 of st. 14259 sub p 14308 u308 14264 trz n 14299 u299 7 14269 tra i 01 14299 u2z9 error routine 14274 sel 2 0500 14279 wr r 14309 u309 14284 tra i 03 14294 u2i4 14289 tr 1 14299 u299 14294 hlt j 0157 14299 tra i 02 14234 u2l4 14304 tr 1 14319 u319 7 7 2 002 14306 + 1 2 002 14308 2 003 14311 157 2 001 14312 | 7 7 routine #158 7 test store instruction. 7 store plus 11. 7 14319 set b 0000 14324 set b 0003 14329 unl 7 14408 u408 reset store field 14334 rad h 14402 u402 rad plus 11 14339 st f 14408 u408 on st, emit a, b bits in cyc 3 14344 set b 0003 14349 lod 8 14405 u405 14354 cmp 4 14408 u408 14359 tre l 14394 u394 7 14364 tra i 01 14394 u3z4 error routine 14369 sel 2 0500 14374 wr r 14409 u409 14379 tra i 03 14389 u3h9 14384 tr 1 14394 u394 14389 hlt j 0158 14394 tra i 02 14319 u3j9 14399 tr 1 14419 u419 to next routine 7 7 2 003 14402 + 11 2 003 14405 +1a 2 003 14408 000 2 003 14411 158 2 001 14412 | Not storing + in first digit 7 7 7 routine #159 7 test store for sup ad carry. 7 14419 set b 0000 14424 set b 0002 14429 unl 7 14501 u501 reset store field 7 14434 lod 8 14496 u496 14439 st f 14501 u501 st =@ ) becomes a lozenge 14444 lod 8 14498 u498 14449 cmp 4 14501 u501 14454 tre l 14489 u489 7 14459 tra i 01 14489 u4y9 error routine 14464 sel 2 0500 14469 wr r 14502 u502 14474 tra i 03 14484 u4h4 14479 tr 1 14489 u489 14484 hlt j 0159 14489 tra i 02 14419 u4j9 14494 tr 1 14514 u514 7 7 2 002 14496 =@ 2 002 14498 =) 2 003 14501 00 2 003 14504 159 2 001 14505 | 7 7 7 routine #160 7 test store instruction 7 14514 set b 0002 14519 lod 8 14608 u608 14524 unl 7 14610 u610 reset store field 14529 rad h 14606 u606 14534 st f 14610 u610 on store, mbr is a blank 14539 set b 0002 when smt is on. 14544 lod 8 14606 u606 14549 cmp 4 14610 u610 14554 tre l 14589 u589 7 14559 tra i 01 14589 u5y9 error routine 14564 sel 2 0500 14569 wr r 14611 u611 14574 tra i 03 14584 u5h4 14579 tr 1 14589 u589 14584 hlt j 0160 14589 tra i 02 14514 u5j4 14594 rcv u 0306 14599 tr 1 01 0204 02 4 14604 tr 1 14619 u619 to next routine 7 7 2 002 14606 + 1 2 002 14608 2 002 14610 2 003 14613 160 2 001 14614 | 7 7 routine #161 7 execute rnd type cycle 1 and 2 7 only. test for no 900 check 7 14619 set b 0001 14624 lod 8 14685 u685 14629 rnd e 0000 14634 trs o 10 14649 uom9 14639 cmp 4 14685 u685 14644 tre l 14679 u679 7 14649 tra i 01 14679 u6x9 error routine 14654 sel 2 0500 14659 wr r 14686 u686 14664 tra i 03 14674 u6g4 14669 tr 1 14679 u679 14674 hlt j 0161 14679 tra i 02 14619 u6j9 14684 tr 1 14694 u694 7 7 2 001 14685 5 2 003 14688 161 2 001 14689 | 7 7 routine #162 7 test round. do type cycle 3 7 to route 1 and 4 to ad. 7 no dec car out. 7 14694 set b 0002 14699 lod 8 14756 u756 14704 rnd e 0001 14709 cmp 4 14755 u755 14714 tre l 14749 u749 7 14719 tra i 01 14749 u7u9 error routine 14724 sel 2 0500 14729 wr r 14757 u757 14734 tra i 03 14744 u7d4 14739 tr 1 14749 u749 14744 hlt j 0162 14749 tra i 02 14694 u6r4 14754 tr 1 14769 u769 to next routine 7 7 2 001 14755 1 2 001 14756 2 2 003 14759 162 2 001 14760 | 7 7 routine #163 7 test round for dec. carry 7 in type cycle 3. 7 14769 rad h 14827 u827 14774 rnd e 0001 14779 sub p 14828 u828 14784 trz n 14819 u819 7 14789 tra i 01 14819 u8/9 error routine 14794 sel 2 0500 14799 wr r 14829 u829 14804 tra i 03 14814 u8a4 14809 tr 1 14819 u819 14814 hlt j 0163 14819 tra i 02 14769 u7o9 14824 tr 1 14839 u839 7 7 2 003 14827 + 15 2 001 14828 +2 2 003 14831 163 2 001 14832 | 7 7 7 routine #164 7 test round instruction 7 dec. carry twice in tc 3. 7 14839 rad h 14898 u898 14844 rnd e 0001 14849 sub p 14900 u900 14854 trz n 14889 u889 7 14859 tra i 01 14889 u8y9 14864 sel 2 0500 14869 wr r 14901 u901 14874 tra i 03 14884 u8h4 14879 tr 1 14889 u889 14884 hlt j 0164 14889 tra i 02 14839 u8l9 14894 tr 1 14909 u909 7 7 2 004 14898 + 096 2 002 14900 +10 2 003 14903 164 2 001 14904 | 7 7 7 routine #165 7 test round for no tf dzt 7 in type cycle 2 or 3. 7 14909 set b 0000 14914 set b 0004 14919 rnd e 0002 14924 trz n 14959 u959 7 14929 tra i 01 14959 u9v9 error routine 14934 sel 2 0500 14939 wr r 14965 u965 14944 tra i 03 14954 u9e4 14949 tr 1 14959 u959 14954 hlt j 0165 14959 tra i 02 14909 u9-9 14964 tr 1 14974 u974 7 7 2 003 14967 165 2 001 14968 | 7 7 7 routine #166 7 test sign instruction for 7 set storage sign plus. 7 14974 rsu q 15026 v026 14979 sgn t 15027 v027 14984 trp m 15019 v019 7 14989 tra i 01 15019 v0/9 14994 sel 2 0500 14999 wr r 15028 v028 15004 tra i 03 15014 v0a4 15009 tr 1 15019 v019 15014 hlt j 0166 15019 tra i 02 14974 u9p4 15024 tr 1 15039 v039 to next routine 7 7 2 002 15026 + 1 2 001 15027 1 2 003 15030 166 2 001 15031 | 7 7 7 routine #167 7 test sigin instruction for 7 set storage sign minus. 7 15039 set b 0001 15044 lod 8 15105 v105 15049 unl 7 15106 v106 reset sign char. 15054 sgn t 15106 v106 15059 trp m 15069 v069 15064 tr 1 15099 v099 7 15069 tra i 01 15099 v0z9 error rotuine 15074 sel 2 0500 15079 wr r 15107 v107 15084 tra i 03 15094 v0i4 15089 tr 1 15099 v099 15094 hlt j 0167 15099 tra i 02 15039 v0l9 15104 tr 1 15119 v119 7 7 2 001 15105 j 2 001 15106 j 2 003 15109 167 2 001 15110 | 7 7 7 routine #168 7 test sgn instruction 7 for turn off dzt. 7 15119 set b 0000 15124 sgn t 15175 v175 15129 trz n 15139 v139 15134 tr 1 15169 v169 7 15139 tra i 01 15169 v1w9 error routine 15144 sel 2 0500 15149 wr r 15176 v176 15154 tra i 03 15164 v1f4 15159 tr 1 15169 v169 15164 hlt j 0168 15169 tra i 02 15119 v1j9 15174 tr 1 15184 v184 to next routine 7 7 2 001 15175 1 2 003 15178 168 2 001 15179 | 7 7 7 routine #169 7 test sgn for sup ad carry and 7 routings to place character 7 back in memory. 7 15184 set b 0001 15189 lod 8 15255 v255 15194 unl 7 15257 v257 reset sgn char. 15199 sgn t 15257 v257 on sgn, change $ to = 15204 lod 8 15257 v257 15209 cmp 4 15256 v256 15214 tre l 15249 v249 7 15219 tra i 01 15249 v2u9 error routine 15224 sel 2 0500 15229 wr r 15258 v258 15234 tra i 03 15244 v2d4 15239 tr 1 15249 v249 15244 hlt j 0169 15249 tra i 02 15184 v1q4 15254 tr 1 15269 v269 7 7 2 001 15255 $ 2 001 15256 = 2 001 15257 $ 2 003 15260 169 2 001 15261 | 7 7 routine #170 7 test sgn for emit blank to 7 memory on mbr bl hyp amp sm. 7 15269 set b 0001 15274 lod 8 15340 v340 15279 unl 7 15342 v342 reset sgn char. 15284 sgn t 15342 v342 on sgn change dash to blank 15289 lod 8 15342 v342 15294 cmp 4 15341 v341 15299 tre l 15334 v334 7 15304 tra i 01 15334 v3t4 error routine 15309 sel 2 0500 15314 wr r 15343 v343 15319 tra i 03 15329 v3b9 15324 tr 1 15334 v334 15329 hlt j 0170 15334 tra i 02 15269 v2o9 15339 tr 1 15354 v354 7 7 2 001 15340 - 2 001 15341 2 001 15342 - 2 003 15345 170 2 001 15346 | 7 7 7 routine #171 7 test sgn for emit a and b bits 7 to storage. 7 15354 sgn t 15415 v415 15359 cmp 4 15415 v415 15364 tre l 15379 v379 15369 cmp 4 15416 v416 15374 tre l 15409 v409 7 15379 tra i 01 15409 v4 9 error routine 15384 sel 2 0500 15389 wr r 15417 v417 15394 tra i 03 15404 v4+4 15399 tr 1 15409 v409 15404 hlt j 0171 15409 tra i 02 15354 v3n4 15414 tr 1 15429 v429 7 7 2 001 15415 1 2 001 15416 + 2 003 15419 171 2 001 15420 | 7 7 routine #172 7 test sgn for emit b bit only 7 to storage. 7 15429 set b 0001 15434 lod 8 15515 v515 15439 unl 7 15517 v517 reset sgn char. 15444 sgn t 15517 v517 15449 cmp 4 15515 v515 15454 tre l 15469 v469 15459 cmp 4 15516 v516 15464 tre l 15499 v499 7 15469 tra i 01 15499 v4z9 error routine 15474 sel 2 0500 15479 wr r 15518 v518 15484 tra i 03 15494 v4i4 15489 tr 1 15499 v499 15494 hlt j 0172 15499 tra i 02 15429 v4k9 15504 rcv u 0306 15509 tr 1 01 0204 02 4 15514 tr 1 15529 v529 to next routine 7 7 2 001 15515 j 2 001 15516 - 2 001 15517 j 2 003 15520 172 2 001 15521 | 7 7 7 routine #173 7 test lfc instruction. lfc 4 7 char. no zones, no c bits, 7 into stor char 0. 7 15529 eem 3 14 0000 0+-0 15534 spc , 0000 15539 set b 0000 reset storage word 15544 set b 0008 to zeros and 15549 lfc , 02 15609 v6-9 lfc 3@05 15554 trs o 11 15569 vnf9 test 901 15559 cmp 4 15617 v617 15564 tre l 15599 v599 7 15569 tra i 01 15599 v5z9 error routine 15574 sel 2 0500 15579 wr r 15618 v618 15584 tra i 03 15594 v5i4 15589 tr 1 15599 v599 15594 hlt j 0173 15599 tra i 02 15529 v5k9 15604 tr 1 15629 v629 7 7 2 005 15609 x3@05 lfc field 2 008 15617 00003@05 correct result 2 003 15620 173 2 001 15621 | 7 7 7 routine #174 7 test lfc instruction. 7 lfc one character, zone 7 only, into stor char 0. 7 15629 eem 3 14 0000 0+-0 15634 spc , 0000 15639 set b 0008 reset storage word 15644 lod 8 15709 v709 to xxxxxxxx 15649 lfc , 02 15701 v7-1 lfc an ampersand 15654 cmp 4 15710 v710 15659 tre l 15694 v694 7 15664 tra i 01 15694 v6z4 error routine 15669 sel 2 0500 15674 wr r 15711 v711 15679 tra i 03 15689 v6h9 15684 tr 1 15694 v694 15689 hlt j 0174 15694 tra i 02 15629 v6k9 15699 tr 1 15719 v719 to next routine 7 7 2 002 15701 x+ lfc character 2 009 15710 xxxxxxxx+ 2 003 15713 174 2 001 15714 | 7 7 7 routine #175 7 test lfc instruction -3 char. 7 lfc a dilroy and two other 7 characters into stor. char 5 7 15719 eem 3 14 0000 0+-0 15724 sb % 12 15791 vg91 make a dilroy 15729 spc , 0005 15734 lfc , 02 15793 v7r3 lfc dilroy, lozenge and gm 15739 set b 0004 set l across stor, mark 15744 cmp 4 15797 v797 generated by dilroy and 15749 tre l 15784 v784 cmp the result 7 15754 tra i 01 15784 v7y4 error routine 15759 sel 2 0500 15764 wr r 15798 v798 15769 tra i 03 15779 v7g9 15774 tr 1 15784 v784 15779 hlt j 0175 15784 tra i 02 15719 v7j9 15789 tr 1 15809 v809 7 7 2 003 15792 -f| 2 001 15793 | 2 003 15796 00| 2 001 15797 | 2 003 15800 175 2 001 15801 | 7 7 routine #176 7 test lfc 2 characters 7 made up of b842 and a842 bits 7 lfc into stor. char. 7 7 15809 eem 3 14 0000 0+-0 15814 sb % 12 15886 vh86 make b842 15819 sb % 12 15887 vh87 make a842 15824 spc , 0007 15829 lfc , 02 15887 v8q7 lfc two char. to test 15834 set b 0002 dilroy recognition 15839 cmp 4 15887 v887 15844 tre l 15879 v879 7 15849 tra i 01 15879 v8x9 error routine 15854 sel 2 0500 15859 wr r 15888 v888 15864 tra i 03 15874 v8g4 15869 tr 1 15879 v879 15874 hlt j 0176 15879 tra i 02 15809 v8-9 15884 tr 1 15899 v899 to next routine 7 7 2 003 15887 00w 2 003 15890 176 2 001 15891 | 7 7 7 routine #177 7 test lfc 5 characters 7 lfc mixed field into 7 storage char. 5. 7 15899 eem 3 14 0000 0+-0 15904 spc , 0005 15909 set b 0000 clear storage 15914 set b 0006 to six zeros 15919 lfc , 02 15980 v9q0 lfc 5 characters 15924 set b 0006 15929 cmp 4 15986 v986 cmp 6 char. 15934 tre l 15969 v969 7 15939 tra i 01 15969 v9w9 error routine 15944 sel 2 0500 15949 wr r 15987 v987 15954 tra i 03 15964 v9f4 15959 tr 1 15969 v969 15964 hlt j 0177 15969 tra i 02 15899 v8r9 15974 tr 1 15999 v999 7 7 2 006 15980 x-, +g 2 006 15986 0-, +g 2 003 15989 177 2 001 15990 | 7 7 7 routine #178 7 test lsb on zones only. 7 lsb 255 blanks and 7 compare them. 7 15999 eem 3 14 0000 0+-0 16004 spc , 0000 reset spc in bank 0 16009 set b 0000 16014 set b 0256 clear bank 0 to zeros 16019 lsb , 04 16414 wu14 lsb blanks 16024 set b 0255 16029 cmp 4 16414 w414 cmp blanks 16034 tre l 16069 w069 7 16039 tra i 01 16069 w0w9 error routine 16044 sel 2 0500 16049 wr r 16075 w075 16054 tra i 03 16064 w0f4 16059 tr 1 16069 w069 16064 hlt j 0178 16069 tra i 02 15999 v9r9 16074 tr 1 16084 w084 to next routine 7 7 2 003 16077 178 2 001 16078 | 7 7 7 routine #179 7 test lsb on dilroy. 7 lsb 255 blanks plus dilroy 7 and test for stor. mark 7 16084 eem 3 14 0000 0+-0 16089 spc , 0000 16094 sb % 12 16415 wd15 make f into dilroy 16099 lsb , 04 16415 wu15 16104 set b 0002 set left across storage mark 16109 cmp 4 16418 w418 generate and cmp vs 00. 16114 tre l 16149 w149 7 16119 tra i 01 16149 w1u9 error routine 16124 sel 2 0500 16129 wr r 16419 w419 16134 tra i 03 16144 w1d4 16139 tr 1 16149 w149 16144 hlt j 0179 16149 tra i 02 16084 w0q4 16154 tr 1 16429 w429 to next routine 7 7 2 050 16204 2 050 16254 2 050 16304 2 050 16354 2 050 16404 2 010 16414 260 blanks for routine 178,179,184 2 004 16418 fx00 2 003 16421 179 2 001 16422 | 7 7 7 routine #180 7 test lsb in bank 1 7 lsb zeros with blocks 7 of 8 other characters 7 on each end of field 7 16429 eem 3 14 0000 0+-0 16434 set b 01 0000 00 0 clear bank 1 16439 set b 01 0255 02v5 16444 unl 7 01 79990 i9z- and unl zeros to mem. field 16449 set b 02 0008 00-8 16454 lod 8 02 16580 w5q0 aktdqz.* 16459 unl 7 02 79742 i7mk unl to left end of field 16464 lod 8 02 16572 w5p2 -+%gpxen 16469 unl 7 02 79990 i9r- unl to right end of field 7 16474 spc , 1730 spc to last word in bank 1 16479 lsb , 04 79990 iz9- lsb from 79990 16484 set b 0016 16489 cmp 4 16580 w580 cmp first and last words 16494 tre l 16504 w504 16499 tr 1 16524 w524 7 16504 lng d 0001 place sm to right. 16509 shr c 0018 shorten past sm on 16514 spc , 0000 left and check zeros. 16519 trz n 16559 w559 7 16524 spc , 0000 reset spc on error 7 16529 tra i 01 16559 w5v9 error routine 16534 sel 2 0500 16539 wr r 16581 w581 16544 tra i 03 16554 w5e4 16549 tr 1 16559 w559 16554 hlt j 0180 16559 tra i 02 16429 w4k9 16564 tr 1 16589 w589 to next routine 7 7 2 008 16572 -+%gpxen first storage word in bank 1 2 008 16580 aktdqz.* last storage word in bank 2 2 003 16583 180 2 001 16584 | 7 7 7 routine #181 7 test ufc using zones only. 7 ufc 2 characters. 7 7 16589 eem 3 14 0000 0+-0 16594 spc , 0000 16599 set b 0000 16604 set b 0003 16609 unl 7 16687 w687 16614 lod 8 16690 w690 lod -+ 16619 ufc , 03 16687 w6h7 do ufc 16624 lod 8 16693 w693 16629 cmp 4 16687 w687 cmp 3 char. in memory 16634 tre l 16669 w669 7 16639 tra i 01 16669 w6w9 error routine 16644 sel 2 0500 16649 wr r 16694 w694 16654 tra i 03 16664 w6f4 16659 tr 1 16669 w669 16664 hlt j 0181 16669 tra i 02 16589 w5q9 16674 rcv u 0306 16679 tr 1 01 0204 02 4 16684 tr 1 16704 w704 to next routine 7 7 2 003 16687 000 ufc area 2 003 16690 x-+ test characters 2 003 16693 0-+ correct result 2 003 16696 181 2 001 16697 | 7 7 16704 eem 3 14 0000 0+-0 routine #182 16709 spc , 0000 test ufc. storage mark 16714 set b 0005 to dilroy generation 16719 lod 8 16834 w834 16724 unl 7 16829 w829 reset mem field to blanks 16729 sb % 12 16838 wh38 make two 16734 sb % 12 16837 wh37 dilroys 16739 set b 0000 16744 set b 0004 place storage marks 16749 set b 0002 in storage char 1,2,4 16754 set b 0001 7 16759 ufc , 03 16829 w8b9 do ufc 16764 trs o 11 16789 wph9 test 901 16769 set b 01 0005 00 5 16774 lod 8 01 16839 w8t9 lod dilroys and 16779 cmp 4 01 16829 w8s9 cmp vs ufc result 16784 tre l 16819 w819 7 16789 tra i 01 16819 w8/9 error routine 16794 sel 2 0500 16799 wr r 16840 w840 16804 tra i 03 16814 w8a4 16809 tr 1 16819 w819 16814 hlt j 0182 16819 tra i 02 16704 w7-4 16824 tr 1 16849 w849 7 7 2 005 16829 ----- ufc area 2 005 16834 5 blanks 2 005 16839 0ff0 correct result 2 003 16842 182 2 001 16843 | error 7 7 16849 eem 3 14 0000 0+-0 routine #183 16854 spc , 0000 test ufc-five characters 16859 set b 0000 16864 set b 0005 16869 unl 7 16935 w935 clear memory field 16874 lod 8 16941 w941 16879 ufc , 03 16935 w9c5 do ufc 16884 cmp 4 16935 w935 compare result 16889 tre l 16924 w924 7 16894 tra i 01 16924 w9s4 error routine 16899 sel 2 0500 16904 wr r 16942 w942 16909 tra i 03 16919 w9a9 16914 tr 1 16924 w924 16919 hlt j 0183 16924 tra i 02 16849 w8m9 16929 tr 1 16954 w954 to next routine 7 7 2 006 16935 x00000 ufc area 2 006 16941 xg8*,a correct result 2 003 16944 183 2 001 16945 | error 7 7 7 routine #184 7 test usb using bank 0. 7 usb a field which has 7 mixed characters in the 7 first and last storage 7 words. rest of bank is zero 7 16954 eem 3 14 0000 0+-0 16959 spc , 0000 16964 set b 0130 16969 lod 8 16414 w414 lod 130 blanks from rout. #178 16974 unl 7 79990 i99- clear lsb area 16979 unl 7 79860 i86- to blanks 16984 set b 0008 16989 lod 8 17132 x132 first storage word 16994 set b 0256 put zeros in rest of bank 16999 spc , 0730 17004 lod 8 17140 x140 last storage word 17009 sb % 12 17132 xa32 make f into dilroy 7 17014 usb , 05 79990 izz- usb into 79990 17019 set b 01 0008 00 8 17024 lod 8 01 17132 x1t2 17029 cmp 4 01 79990 i9z- cmp first word result 17034 tre l 17044 x044 17039 tr 1 17079 x079 17044 lod 8 01 17140 x1u0 17049 cmp 4 01 79742 i7uk 17054 tre l 17064 x064 17059 tr 1 17079 x079 7 17064 set b 01 0240 02u0 test for zeros 17069 lod 8 01 79982 i9yk in rest of memory field 17074 trz n 01 17109 x1 9 at 79982 7 17079 tra i 01 17109 x1 9 error routine 17084 sel 2 0500 17089 wr r 17141 x141 17094 tra i 03 17104 x1+4 17099 tr 1 17109 x109 17104 hlt j 0184 17109 tra i 02 16954 w9n4 17114 rcv u 0306 17119 tr 1 01 0204 02 4 17124 tr 1 17149 x149 to next routine 7 2 008 17132 akuhcnxf 2 008 17140 +-.#%+70 2 003 17143 184 2 001 17144 | error 7 7 7 routine #185 7 execute ntr type cycle 1 only. 7 test no transfer, no 900 check 7 17149 rad h 17206 x206 17154 ntr x 17169 x169 17159 trs o 10 17169 xjo9 17164 tr 1 17199 x199 7 17169 tra i 01 17199 x1z9 error routine 17174 sel 2 0500 17179 wr r 17207 x207 17184 tra i 03 17194 x1i4 17189 tr 1 17199 x199 17194 hlt j 0185 17199 tra i 02 17149 x1m9 17204 tr 1 17219 x219 7 7 2 002 17206 + 0 2 003 17209 185 2 001 17210 | 7 7 7 routine #186 7 test ntr for no transfer on 7 zero field length, or on 7 non-zero character. 7 17219 set b 0000 17224 ntr x 17244 x244 17229 rad h 17282 x282 17234 ntr x 17244 x244 17239 tr 1 17274 x274 7 17244 tra i 01 17274 x2x4 error routine 17249 sel 2 0500 17254 wr r 17283 x283 17259 tra i 03 17269 x2f9 17264 tr 1 17274 x274 17269 hlt j 0186 17274 tra i 02 17219 x2j9 17279 tr 1 17294 x294 to next routine 7 7 2 003 17282 + 10 2 003 17285 186 2 001 17286 | 7 7 7 routine #187 7 test ntr for transfer 7 on zero char. in tc 2. 7 17294 set b 0000 17299 set b 0002 17304 ntr x 17339 x339 7 17309 tra i 01 17339 x3t9 17314 sel 2 0500 17319 wr r 17345 x345 17324 tra i 03 17334 x3c4 17329 tr 1 17339 x339 17334 hlt j 0187 17339 tra i 02 17294 x2r4 17344 tr 1 17354 x354 7 7 2 003 17347 187 2 001 17348 | 7 7 7 routine #188 7 test ntr for removal of 7 4 zeros fromf storage field 7 17354 rad h 17451 x451 17359 rad h 01 17451 x4v1 17364 set b 01 0005 00 5 17369 ntr x 01 17379 x3x9 do ntr 4 times 17374 tr 1 17389 x389 17379 add g 17451 x451 17384 tr 1 17369 x369 17389 cmp 4 17453 x453 17394 tre l 17404 x404 17399 tr 1 17414 x414 17404 cmp 4 01 17452 x4v2 test for a one left in 17409 tre l 01 17444 x4u4 storage field. 7 17414 tra i 01 17444 x4u4 error routine 17419 sel 2 0500 17424 wr r 17454 x454 17429 tra i 03 17439 x4c9 17434 tr 1 17444 x444 17439 hlt j 0188 17444 tra i 02 17354 x3n4 17449 tr 1 17464 x464 to next routine 7 7 2 002 17451 a 2 002 17453 15 2 003 17456 188 2 001 17457 | 7 7 7 routine #189 7 test ntr for sup ad carry 7 and zn ad out in type cycle 2. 7 17464 set b 0002 17469 lod 8 17561 x561 lod #0 17474 ntr x 17514 x514 17479 cmp 4 17561 x561 cmp #0 17484 tre l 17494 x494 17489 tr 1 17514 x514 7 17494 lod 8 17563 x563 lod +0 17499 ntr x 17514 x514 17504 cmp 4 17563 x563 cmp +0 17509 tre l 17544 x544 7 17514 tra i 01 17544 x5u4 error routine 17519 sel 2 0500 17524 wr r 17564 x564 17529 tra i 03 17539 x5c9 17534 tr 1 17544 x544 17539 hlt j 0189 17544 tra i 02 17464 x4o4 17549 rcv u 0306 17554 tr 1 01 0204 02 4 17559 tr 1 17574 x574 7 7 2 002 17561 #0 2 002 17563 +0 2 003 17566 189 2 001 17567 | 7 7 7 routine #190 7 execute spr and test for 7 emit blank and no 900 check. 7 17574 rad h 17657 x657 17579 unl 7 17659 x659 reset spr field 17584 set b 0000 17589 spr 5 17659 x659 17594 trs o 10 17619 xoj9 17599 set b 0001 17604 lod 8 17655 x655 17609 cmp 4 17659 x659 17614 tre l 17649 x649 7 17619 tra i 01 17649 x6u9 error routine 17624 sel 2 0500 17629 wr r 17660 x660 17634 tra i 03 17644 x6d4 17639 tr 1 17649 x649 17644 hlt j 0190 17649 tra i 02 17574 x5p4 17654 tr 1 17669 x669 to next routine 7 7 2 003 17657 0+ 2 002 17659 2 003 17662 190 2 001 17663 | error 7 7 7 routine #191 7 test spr. place 2 zeros in 7 memory in tc 1. replace zeros 7 with blanks in tc 2 and 3. 7 17669 set b 0000 17674 set b 0002 17679 spr 5 17746 x746 17684 set b 0003 17689 lod 8 17742 x742 17694 cmp 4 17746 x746 17699 tre l 17734 x734 7 17704 tra i 01 17734 x7t4 error routine 17709 sel 2 0500 17714 wr r 17747 x747 17719 tra i 03 17729 x7b9 17724 tr 1 17734 x734 17729 hlt j 0191 17734 tra i 02 17669 x6o9 17739 tr 1 17759 x759 7 7 2 003 17742 2 004 17746 2 003 17749 191 2 001 17750 | error 7 7 7 routine #192 7 test spr on storage equal 7 minus 1. emit b bit in tc 1. 7 17759 set b 0003 17764 lod 8 17844 x844 17769 unl 7 17849 x849 reset spr field 17774 rsu q 17841 x841 17779 spr 5 17849 x849 17784 set b 0002 17789 lod 8 17846 x846 17794 cmp 4 17849 x849 17799 tre l 17834 x834 7 17804 tra i 01 17834 x8t4 error routine 17809 sel 2 0500 17814 wr r 17850 x850 17819 tra i 03 17829 x8b9 17824 tr 1 17834 x834 17829 hlt j 0192 17834 tra i 02 17759 x7n9 17839 tr 1 17859 x859 to next routine 7 7 2 002 17841 + 1 2 005 17846 1- 2 003 17849 2 003 17852 192 2 001 17853 | error 7 7 7 routine #193 7 test spr with zeros stored 7 into memory field containing 7 period and commas. 7 17859 set b 0005 17864 lod 8 17949 x949 17869 unl 7 17961 x961 reset spr field 17874 set b 0000 17879 set b 0002 17884 spr 5 17961 x961 17889 set b 0006 17894 lod 8 17955 x955 17899 cmp 4 17961 x961 17904 tre l 17939 x939 7 17909 tra i 01 17939 x9t9 error routine 17914 sel 2 0500 17919 wr r 17962 x962 17924 tra i 03 17934 x9c4 17929 tr 1 17939 x939 17934 hlt j 0193 17939 tra i 02 17859 x8n9 17944 tr 1 17974 x974 7 7 2 005 17949 ,..11 2 006 17955 ..0 2 006 17961 2 003 17964 193 2 001 17965 | error 7 7 7 routine #194 7 test spr for route zn ad out 7 by storing non-numerics 7 17974 set b 0003 17979 lod 8 18047 y047 17984 spr 5 18055 y055 17989 set b 0004 17994 lod 8 18051 y051 17999 cmp 4 18055 y055 18004 tre l 18039 y039 7 18009 tra i 01 18039 y0t9 error routine 18014 sel 2 0500 18019 wr r 18056 y056 18024 tra i 03 18034 y0c4 18029 tr 1 18039 y039 18034 hlt j 0194 18039 tra i 02 17974 x9p4 18044 tr 1 18064 y064 to next routine 7 7 2 003 18047 a+- 2 004 18051 a+- 2 004 18055 2 003 18058 194 2 001 18059 | error 7 7 7 routine #195 7 test spr for sup ad carry. 7 18064 set b 0001 18069 lod 8 18135 y135 18074 spr 5 18137 y137 18079 cmp 4 18136 y136 18084 tre l 18119 y119 7 18089 tra i 01 18119 y1/9 error routine 18094 sel 2 0500 18099 wr r 18138 y138 18104 tra i 03 18114 y1a4 18109 tr 1 18119 y119 18114 hlt j 0195 18119 tra i 02 18064 y0o4 18124 rcv u 0306 18129 tr 1 01 0204 02 4 18134 tr 1 18804 y804 7 7 2 001 18135 # 2 002 18137 2 003 18140 195 2 001 18141 | error 7 7 7 routine #196 7 execute adm and test for 7 memory field unchanged 7 and no 900 check 7 7 18804 rad h 18881 y881 18809 unl 7 18883 y883 reset adm field 18814 set b 0000 18819 adm 6 18883 y883 18824 trs o 10 18844 yqm4 18829 rad h 18881 y881 18834 cmp 4 18883 y883 18839 tre l 18874 y874 7 18844 tra i 01 18874 y8x4 error routine 18849 sel 2 0500 18854 wr r 18884 y884 18859 tra i 03 18869 y8f9 18864 tr 1 18874 y874 18869 hlt j 0196 18874 tra i 02 18804 y8-4 18879 tr 1 18894 y894 to next routine 7 7 2 002 18881 + 1 2 002 18883 2 003 18886 196 2 001 18887 | 7 7 7 routine #197 7 test signed adm. signs alike 7 plus. adm +1 to +1. 7 18894 rad h 18961 y961 18899 st f 18965 y965 reset memory field 18904 adm 6 18965 y965 18909 lod 8 18963 y963 18914 cmp 4 18965 y965 18919 tre l 18954 y954 7 18924 tra i 01 18954 y9v4 error routine 18929 sel 2 0500 18934 wr r 18966 y966 18939 tra i 03 18949 y9d9 18944 tr 1 18954 y954 18949 hlt j 0197 18954 tra i 02 18894 y8r4 18959 tr 1 18974 y974 7 7 2 002 18961 + 1 2 002 18963 + 2 2 002 18965 2 003 18968 197 2 001 18969 | error 7 7 7 routine #198 7 test signed adm. signs alike 7 minus. adm -1 to -1. 7 18974 rsu q 19041 z041 18979 st f 19045 z045 reset memory field 18984 adm 6 19045 z045 18989 lod 8 19043 z043 18994 cmp 4 19045 z045 18999 tre l 19034 z034 7 19004 tra i 01 19034 z0t4 error routine 19009 sel 2 0500 19014 wr r 19046 z046 19019 tra i 03 19029 z0b9 19024 tr 1 19034 z034 19029 hlt j 0198 19034 tra i 02 18974 y9p4 19039 tr 1 19054 z054 to next routine 7 7 2 002 19041 + 1 2 002 19043 - 2 2 002 19045 2 003 19048 198 2 001 19049 | error 7 7 7 routine #199 7 test signed adm. signs 7 opposite. adm -1 to +1. 7 compl. addition and tc 1 only. 7 19054 rad h 19126 z126 19059 st f 19130 z130 reset memory field 19064 rsu q 19126 z126 19069 adm 6 19130 z130 19074 lod 8 19128 z128 19079 cmp 4 19130 z130 19084 tre l 19119 z119 7 19089 tra i 01 19119 z1/9 error routine 19094 sel 2 0500 19099 wr r 19131 z131 19104 tra i 03 19114 z1a4 19109 tr 1 19119 z119 19114 hlt j 0199 19119 tra i 02 19054 z0n4 19124 tr 1 19139 z139 7 7 2 002 19126 + 1 2 002 19128 + 0 2 002 19130 2 003 19133 199 2 001 19134 | error 7 7 7 routine #200 7 test signed adm, signs 7 opposite. adm +2 to -2. 7 compl. addition and tc 1 only. 7 19139 rsu q 19211 z211 19144 st f 19215 z215 reset memory field 19149 rad h 19211 z211 19154 adm 6 19215 z215 19159 lod 8 19213 z213 19164 cmp 4 19215 z215 19169 tre l 19204 z204 7 19174 tra i 01 19204 z2 4 error routine 19179 sel 2 0500 19184 wr r 19216 z216 19189 tra i 03 19199 z1i9 19194 tr 1 19204 z204 19199 hlt j 0200 19204 tra i 02 19139 z1l9 19209 tr 1 19224 z224 to next routine 7 7 2 002 19211 + 2 2 002 19213 - 0 2 002 19215 2 003 19218 200 2 001 19219 | error 7 7 7 routine #301 7 test signed adm. signs 7 opposite. adm -22 to +33. 7 compl. addition and tc 1 only. 7 19224 rad h 19297 z297 19229 st f 19306 z306 reset memory field 19234 rsu q 19300 z300 19239 adm 6 19306 z306 19244 lod 8 19303 z303 19249 cmp 4 19306 z306 19254 tre l 19289 z289 7 19259 tra i 01 19289 z2y9 error routine 19264 sel 2 0500 19269 wr r 19307 z307 19274 tra i 03 19284 z2h4 19279 tr 1 19289 z289 19284 hlt j 0201 19289 tra i 02 19224 z2k4 19294 tr 1 19319 z319 7 7 2 003 19297 + 33 2 003 19300 + 22 2 003 19303 + 11 2 003 19306 2 003 19309 201 2 001 19310 | 7 7 7 routine #202 7 test signed adm, signs 7 opposite. adm -33 to +22 7 compl. mbr in type cycle 2. 7 19319 rad h 19392 z392 19324 st f 19401 z401 reset memory field 19329 rsu q 19395 z395 19334 adm 6 19401 z401 19339 lod 8 19398 z398 19344 cmp 4 19401 z401 19349 tre l 19384 z384 7 19354 tra i 01 19384 z3y4 error routine 19359 sel 2 0500 19364 wr r 19402 z402 19369 tra i 03 19379 z3g9 19374 tr 1 19384 z384 19379 hlt j 0202 19384 tra i 02 19319 z3j9 19389 tr 1 19414 z414 to next routine 7 7 2 003 19392 + 23 2 003 19395 + 33 2 003 19398 - 10 2 003 19401 2 003 19404 202 2 001 19405 | 7 7 7 routine #203 7 test signed adm, signs 7 opposite. adm +33 to -22 7 compl. mbr in type cycle 2. 7 19414 rsu q 19487 z487 19419 st f 19496 z496 reset memory field 19424 rad h 19490 z490 19429 adm 6 19496 z496 19434 lod 8 19493 z493 19439 cmp 4 19496 z496 19444 tre l 19479 z479 7 19449 tra i 01 19479 z4x9 error routine 19454 sel 2 0500 19459 wr r 19497 z497 19464 tra i 03 19474 z4g4 19469 tr 1 19479 z479 19474 hlt j 0203 19479 tra i 02 19414 z4j4 19484 tr 1 19509 z509 7 7 2 003 19487 + 22 2 003 19490 + 33 2 003 19493 + 11 2 003 19496 2 003 19499 203 2 001 19500 | 7 7 7 routine #204 7 test signed adm. signs 7 opposite. compl. mbr 7 equal 1234567 in tc 2. 7 19509 rad h 19587 z587 19514 st f 19611 z611 reset mem field to -1111111 19519 lod 8 19595 z595 store field to +9876544 19524 adm 6 19611 z611 19529 lod 8 19603 z603 lod and cmp answer 19534 cmp 4 19611 z611 which should be +8765433 19539 tre l 19574 z574 7 19544 tra i 01 19574 z5x4 error routine 19549 sel 2 0500 19554 wr r 19612 z612 19559 tra i 03 19569 z5f9 19564 tr 1 19574 z574 19569 hlt j 0204 19574 tra i 02 19509 z5-9 19579 tr 1 19624 z624 to next routine 7 7 2 008 19587 x111111j 2 008 19595 x9876544 2 008 19603 x876543c 2 008 19611 x adm field 2 003 19614 204 2 001 19615 | 7 7 7 routine #205 7 test unsigned adm, aux 1 7 tgr is on in type cycle 1 7 adm 1 to 1. 7 19624 rad h 19691 z691 19629 unl 7 19694 z694 reset memory field 19634 adm 6 19694 z694 19639 lod 8 19692 z692 19644 cmp 4 19694 z694 19649 tre l 19684 z684 7 19654 tra i 01 19684 z6y4 error routine 19659 sel 2 0500 19664 wr r 19695 z695 19669 tra i 03 19679 z6g9 19674 tr 1 19684 z684 19679 hlt j 0205 19684 tra i 02 19624 z6k4 19689 tr 1 19704 z704 7 7 2 002 19691 + 1 2 001 19692 2 2 002 19694 2 003 19697 205 2 001 19698 | 7 7 7 routine #206 7 test unsigned adm, tc 1 only 7 with aux 1 on. 7 adm an ampersand to a one. 7 19704 rad h 19778 z778 19709 unl 7 19780 z780 reset memory field 19714 sgn t 19780 z780 19719 adm 6 19780 z780 19724 lod 8 19778 z778 19729 cmp 4 19780 z780 19734 tre l 19769 z769 7 19739 tra i 01 19769 z7w9 error routine 19744 sel 2 0500 19749 wr r 19781 z781 19754 tra i 03 19764 z7f4 19759 tr 1 19769 z769 19764 hlt j 0206 19769 tra i 02 19704 z7-4 19774 tr 1 19789 z789 to next routine 7 7 2 004 19778 a 2 002 19780 2 003 19783 206 2 001 19784 | 7 7 7 routine #207 7 TEST unsigned adm. tc 1 only 7 with aux 1 on. 7 adm 088 to 077. 7 19789 rad h 19863 z863 19794 unl 7 19873 z873 reset memory field 19799 lod 8 19866 z866 19804 adm 6 19873 z873 19809 lod 8 19869 z869 19814 cmp 4 19873 z873 19819 tre l 19854 z854 7 19824 tra i 01 19854 z8v4 error routine 19829 sel 2 0500 19834 wr r 19874 z874 19839 tra i 03 19849 z8d9 19844 tr 1 19854 z854 19849 hlt j 0207 19854 tra i 02 19789 z7q9 19859 tr 1 19884 z884 7 7 2 007 19866 x07g088 2 003 19869 165 2 004 19873 2 003 19876 207 2 001 19877 | 7 7 7 routine #208 7 test unsigned adm, tc 1 only 7 with aux 1 on. 7 adm blanks to blanks 7 19884 set b 0002 19889 lod 8 19956 z956 reset memory field 19894 unl 7 19961 z961 19899 adm 6 19961 z961 19904 lod 8 19958 z958 19909 cmp 4 19961 z961 19914 tre l 19949 z949 7 19919 tra i 01 19949 z9u9 error routine 19924 sel 2 0500 19929 wr r 19962 z962 19934 tra i 03 19944 z9d4 19939 tr 1 19949 z949 19944 hlt j 0208 19949 tra i 02 19884 z8q4 19954 tr 1 20054 -054 to next routine 7 7 2 002 19956 2 002 19958 -- 2 002 19961 2 003 19964 208 2 001 19965 | 7 7 7 routine #209 7 test unsigned adm. tc 1 only 7 with aux 1 on. zone addition 7 and zone carry. 7 20054 set b 0003 20059 lod 8 20132 -132 20064 unl 7 20142 -142 reset memory field 20069 lod 8 20135 -135 20074 adm 6 20142 -142 20079 lod 8 20138 -138 20084 cmp 4 20142 -142 20089 tre l 20124 -124 7 20094 tra i 01 20124 -1s4 error routine 20099 sel 2 0500 20104 wr r 20143 -143 20109 tra i 03 20119 -1a9 20114 tr 1 20124 -124 20119 hlt j 0209 20124 tra i 02 20054 -0n4 20129 tr 1 20154 -154 7 7 2 003 20132 aa 2 003 20135 bbb 2 003 20138 cc2 2 004 20142 2 003 20145 209 2 001 20146 | 7 7 7 routine #210 7 test unsigned adm, type 7 cycle 3 with aux 3 tgr off 7 adm 6 to 6 7 20154 set b 0001 20159 lod 8 20225 -225 20164 unl 7 20228 -228 reset memory field 20169 adm 6 20228 -228 20174 lod 8 20226 -226 20179 cmp 4 20228 -228 20184 tre l 20219 -219 7 20189 tra i 01 20219 -2/9 error routine 20194 sel 2 0500 20199 wr r 20229 -229 20204 tra i 03 20214 -2a4 20209 tr 1 20219 -219 20214 hlt j 0210 20219 tra i 02 20154 -1n4 20224 tr 1 20239 -239 to next routine 7 7 2 001 20225 6 2 001 20226 s 2 002 20228 2 003 20231 210 2 001 20232 | 7 7 7 routine #211 7 test unsigned adm, type 7 cycle 3 with aux 3 tgr on. 7 adm 2+ to zs 7 20239 set b 0002 20244 lod 8 20326 -326 20249 unl 7 20335 -335 reset memory field 20254 lod 8 20328 -328 20259 adm 6 20335 -335 20264 lod 8 20330 -330 20269 cmp 4 20335 -335 20274 tre l 20309 -309 7 20279 tra i 01 20309 -3 9 20284 sel 2 0500 20289 wr r 20336 -336 20294 tra i 03 20304 -3+4 20299 tr 1 20309 -309 20304 hlt j 0211 20309 tra i 02 20239 -2l9 20314 rcv u 0306 20319 tr 1 01 0204 02 4 20324 tr 1 20344 -344 7 7 2 002 20326 zs 2 002 20328 2+ 2 002 20330 a2 2 005 20335 2 003 20338 211 2 001 20339 | 7 7 7 routine #212 7 execute mpy tc 1 and 5 only. 7 test for no 900 check. 7 test for replacement of 7 stor. mark with a zero. 7 20344 eem 3 14 0000 0+-0 20349 spc , 0000 20354 set b 0001 place stor. marks 20359 set b 0000 in multiplier. 20364 mpy v 20436 -436 20369 spc , 0000 20374 trs o 10 20399 -lr9 20379 cmp 4 20441 -441 check for multiplier 20384 tre l 20399 -399 not equal stor. mark 20389 cmp 4 20437 -437 and equal zero after mpy. 20394 tre l 20429 -429 7 20399 tra i 01 20429 -4s9 error routine 20404 sel 2 0500 20409 wr r 20438 -438 20414 tra i 03 20424 -4b4 20419 tr 1 20429 -429 20424 hlt j 0212 20429 tra i 02 20344 -3m4 20434 tr 1 20449 -449 7 7 2 002 20436 + 0 2 001 20437 0 2 003 20440 212 2 001 20441 | 7 7 7 routine #213 7 do mpy type cycles 1,2,3,4,5 7 20449 rad h 20501 -501 20454 mpy v 20501 -501 20459 trz n 20494 -494 7 20464 tra i 01 20494 -4z4 error routine 20469 sel 2 0500 20474 wr r 20502 -502 20479 tra i 03 20489 -4h9 20484 tr 1 20494 -494 20489 hlt j 0213 20494 tra i 02 20449 -4m9 20499 tr 1 20514 -514 to next routine 7 7 2 002 20501 + 0 2 003 20504 213 2 001 20505 | 7 7 20514 rad h 20566 -566 routine #214 20519 mpy v 20567 -567 test mpy for turn on dzt. 20524 trz n 20559 -559 7 20529 tra i 01 20559 -5v9 error routine 20534 sel 2 0500 20539 wr r 20568 -568 20544 tra i 03 20554 -5e4 20549 tr 1 20559 -559 20554 hlt j 0214 20559 tra i 02 20514 -5j4 20564 tr 1 20579 -579 7 7 2 002 20566 + 1 2 001 20567 +0 2 003 20570 214 2 001 20571 | 7 7 20579 rsu q 20631 -631 routine #215 20584 mpy v 20632 -632 test mpy for set sign plus 20589 trp m 20624 -624 7 20594 tra i 01 20624 -6s4 error routine 20599 sel 2 0500 20604 wr r 20633 -633 20609 tra i 03 20619 -6a9 20614 tr 1 20624 -624 20619 hlt j 0215 20624 tra i 02 20579 -5p9 20629 tr 1 20644 -644 7 7 2 002 20631 + 1 2 001 20632 +0 2 003 20635 215 2 001 20636 | 7 7 20644 rad h 20701 -701 routine #216 20649 mpy v 20701 -701 test mpy for turn off dzt. 20654 trz n 20664 -664 20659 tr 1 20694 -694 7 20664 tra i 01 20694 -6z4 error routine 20669 sel 2 0500 20674 wr r 20702 -702 20679 tra i 03 20689 -6h9 20684 tr 1 20694 -694 20689 hlt j 0216 20694 tra i 02 20644 -6m4 20699 tr 1 20714 -714 to next routine 7 7 2 002 20701 + 1 2 003 20704 216 2 001 20705 | 7 7 20714 rad h 20766 -766 routine #217 20719 MPY V 20766 -766 test mpy signs alike minus 20724 trp m 20759 -759 for set sign plus. 7 20729 tra i 01 20759 -7v9 error routine 20734 sel 2 0500 20739 wr r 20767 -767 20744 tra i 03 20754 -7e4 20749 tr 1 20759 -759 20754 hlt j 0217 20759 tra i 02 20714 -7j4 20764 tr 1 20779 -779 7 7 2 002 20766 - 1 2 003 20769 217 2 001 20770 | 7 7 20779 rsu q 20836 -836 routine #218 20784 mpy v 20836 -836 test mpy signs opposite 20789 trp m 20799 -799 for set sign minus. 20794 tr 1 20829 -829 7 20799 tra i 01 20829 -8s9 error routine 20804 sel 2 0500 20809 wr r 20837 -837 20814 tra i 03 20824 -8b4 20819 tr 1 20829 -829 20824 hlt j 0218 20829 tra i 02 20779 -7p9 20834 tr 1 20849 -849 7 7 2 002 20836 - 1 2 003 20839 218 2 001 20840 | 7 7 20849 rad h 20906 -906 routine #219 20854 mpy v 20906 -906 test mpy instruction routings. 20859 cmp 4 20908 -908 mpy 1 by 1 and check. 20864 tre l 20899 -899 7 20869 tra i 01 20899 -8z9 error routine 20874 sel 2 0500 20879 wr r 20909 -909 20884 tra i 03 20894 -8i4 20889 tr 1 20899 -899 20894 hlt j 0219 20899 tra i 02 20849 -8m9 20904 tr 1 20919 -919 to next routine 7 7 2 002 20906 + 1 2 002 20908 01 2 003 20911 219 2 001 20912 | 7 7 7 routine #220 7 test mpy and related adder 7 inputs. mpy zero by 2. 7 20919 rad h 20971 -971 20924 mpy v 20972 -972 tn mc 2a, route sel 2 mpl 20929 trz n 20964 -964 when mbr is a zero. 7 20934 tra i 01 20964 -9w4 error routine 20939 sel 2 0500 20944 wr r 20973 -973 20949 tra i 03 20959 -9e9 20954 tr 1 20964 -964 20959 hlt j 0220 20964 tra i 02 20919 -9j9 20969 tr 1 20984 -984 7 7 2 002 20971 + 2 2 001 20972 +0 2 003 20975 220 2 001 20976 | 7 7 7 routine #221 7 test mpy and related adder 7 inputs. mpy 1 by 2. 7 20984 rad h 21041 j041 20989 mpy v 21042 j042 tn mc 2a, route sel 2 mpl 20994 cmp 4 21044 j044 when mbr equals 1. 20999 tre l 21034 j034 7 21004 tra i 01 21034 j0t4 error routine 21009 sel 2 0500 21014 wr r 21045 j045 21019 tra i 03 21029 j0b9 21024 tr 1 21034 j034 21029 hlt j 0221 21034 tra i 02 20984 -9q4 21039 tr 1 21054 j054 to next routine 7 7 2 002 21041 + 2 2 001 21042 +1 2 002 21044 02 2 003 21047 221 2 001 21048 | 7 7 7 routine #222 7 test mpy and related adder 7 inputs. mpy 2 by 2. 7 7 21054 rad h 21111 j111 21059 mpy v 21111 j111 tn mc 2a, route sel 2 mpl 21064 cmp 4 21113 j113 when mbr equals 2. 21069 tre l 21104 j104 7 21074 tra i 01 21104 j1 4 errror routine 21079 sel 2 0500 21084 wr r 21114 j114 21089 tra i 03 21099 j0i9 21094 tr 1 21104 j104 21099 hlt j 0222 21104 tra i 02 21054 j0n4 21109 tr 1 21124 j124 7 7 2 002 21111 + 2 2 002 21113 04 2 003 21116 222 2 001 21117 | 7 7 7 routine #223 7 test mpy and related adder 7 inputs. mpy 4 by 2. 7 21124 rad h 21181 j181 21129 mpy v 21182 j182 tn mc 2a, route sel 2 mpl 21134 cmp 4 21184 j184 when mbr equals 4. 21139 tre l 21174 j174 7 21144 tra i 01 21174 j1x4 error routine 21149 sel 2 0500 21154 wr r 21185 j185 21159 tra i 03 21169 j1f9 21164 tr 1 21174 j174 21169 hlt j 0223 21174 tra i 02 21124 j1k4 21179 tr 1 21194 j194 to next routine 7 7 2 002 21181 + 2 2 001 21182 +4 2 002 21184 08 2 003 21187 223 2 001 21188 | 7 7 7 routine #224 7 test mpy and related adder 7 inputs. mpy 5 by 2. 7 21194 rad h 21251 j251 21199 mpy v 21252 j252 tn mc 2a. route sel 2 mpl 21204 cmp 4 21254 j254 mbr equal 5 - turn on doub car 21209 tre l 21244 j244 7 21214 tra i 01 21244 j2u4 error routine 21219 sel 2 0500 21224 wr r 21255 j255 21229 tra i 03 21239 j2c9 21234 tr 1 21244 j244 21239 hlt j 0224 21244 tra i 02 21194 j1r4 21249 tr 1 21264 j264 7 7 2 002 21251 + 2 2 001 21252 +5 2 002 21254 10 2 003 21257 224 2 001 21258 | 7 7 7 routine #225 7 test mpy and related adder 7 inputs. mpy 3 by 2 and 8 by 2. 7 21264 rad h 21346 j346 21269 mpy v 21347 j347 tn mc 2a, route sel 2 mpl 21274 cmp 4 21349 j349 when mbr equal 3. 21279 tre l 21289 j289 21284 tr 1 21309 j309 7 21289 rad h 21346 j346 21294 mpy v 21351 j351 tn mc 2a, route sel 2 mpl 21299 cmp 4 21353 j353 mbr equal 8 turns on doub., car 21304 tre l 21339 j339 7 21309 tra i 01 21339 j3t9 error routine 21314 sel 2 0500 21319 wr r 21354 j354 21324 tra i 03 21334 j3c4 21329 tr 1 21339 j339 21334 hlt j 0225 21339 tra i 02 21264 j2o4 21344 tr 1 21364 j364 to next routine 7 7 2 002 21346 + 2 2 001 21347 +3 2 002 21349 06 2 002 21351 + 8 2 002 21353 16 2 003 21356 225 2 001 21357 | 7 7 7 routine #226 7 test mpy and related adder 7 inputs. mpy 6 by 2 and 9 by 2 7 21364 rad h 21446 j446 21369 mpy v 21447 j447 tn mc 2a, route sel 2 mpl. 21374 cmp 4 21449 j449 mbr equal 6 turns on doub car. 21379 tre l 21389 j389 21384 tr 1 21409 j409 7 21389 rad h 21446 j446 21394 mpy v 21451 j451 tn mc 2a, route sel 2 mpl. 21399 cmp 4 21453 j453 mbr equal 9 turns on doub car 21404 tre l 21439 j439 7 21409 tra i 01 21439 j4t9 error routine 21414 sel 2 0500 21419 wr r 21454 j454 21424 tra i 03 21434 j4c4 21429 tr 1 21439 j439 21434 hlt j 0226 21439 tra i 02 21364 j3o4 21444 tr 1 21464 j464 7 7 2 002 21446 + 2 2 001 21447 +6 2 002 21449 12 2 002 21451 + 9 2 002 21453 18 2 003 21456 226 2 001 21457 | 7 7 7 routine #227 7 test mpy and related adder 7 inputs. mpy zero by 4. 7 21464 rad h 21516 j516 21469 mpy v 21517 j517 tn mc 2a and mc 2b. 21474 trz n 21509 j509 7 21479 tra i 01 21509 j5 9 error routine 21484 sel 2 0500 21489 wr r 21518 j518 21494 tra i 03 21504 j5+4 21499 tr 1 21509 j509 21504 hlt j 0227 21509 tra i 02 21464 j4o4 21514 tr 1 21529 j529 to next routine 7 7 2 002 21516 + 4 2 001 21517 +0 2 003 21520 227 2 001 21521 | 7 7 7 routine #228 7 test mpy and related adder 7 inputs. mpy 1 by 4. 7 21529 rad h 21586 j586 21534 mpy v 21587 j587 tn mc 2a and 2b. 21539 cmp 4 21589 j589 21544 tre l 21579 j579 7 21549 tra i 01 21579 j5x9 error routine 21554 sel 2 0500 21559 wr r 21590 j590 21564 tra i 03 21574 j5g4 21569 tr 1 21579 j579 21574 hlt j 0228 21579 tra i 02 21529 j5k9 21584 tr 1 21599 j599 7 7 2 002 21586 + 4 2 001 21587 +1 2 002 21589 04 2 003 21592 228 2 001 21593 | 7 7 7 routine #229 7 test mpy and related adder 7 inputs. mpy 2 by 4. 7 21599 rad h 21656 j656 21604 mpy v 21657 j657 tn mc 2a and mc 2b. 21609 cmp 4 21659 j659 21614 tre l 21649 j649 7 21619 tra i 01 21649 j6u9 error routine 21624 sel 2 0500 21629 wr r 21660 j660 21634 tra i 03 21644 j6d4 21639 tr 1 21649 j649 21644 hlt j 0229 21649 tra i 02 21599 j5r9 21654 tr 1 21669 j669 to next routine 7 7 2 002 21656 + 4 2 001 21657 +2 2 002 21659 08 2 003 21662 229 2 001 21663 | 7 7 7 routine #230 7 test mpy and related adder 7 inputs. mpy 5 by 4. 7 21669 rad h 21726 j726 21674 mpy v 21727 j727 tn and use mc 2a, mc 2b 21679 cmp 4 21729 j729 and doub car. 21684 tre l 21719 j719 7 21689 tra i 01 21719 j7/9 error routine 21694 sel 2 0500 21699 wr r 21730 j730 21704 tra i 03 21714 j7a4 21709 tr 1 21719 j719 21714 hlt j 0230 21719 tra i 02 21669 j6o9 21724 tr 1 21739 j739 7 7 2 002 21726 + 4 2 001 21727 +5 2 002 21729 20 2 003 21732 230 2 001 21733 | 7 7 7 routine #231 7 test mpy and related adder 7 inputs. mpy 4 by 4. 7 21739 rad h 21796 j796 21744 mpy v 21796 j796 tn mc 2a, mc 2b. adder 21749 cmp 4 21798 j798 carry to get result of 16. 21754 tre l 21789 j789 7 21759 tra i 01 21789 j7y9 error routine 21764 sel 2 0500 21769 wr r 21799 j799 21774 tra i 03 21784 j7h4 21779 tr 1 21789 j789 21784 hlt j 0231 21789 tra i 02 21739 j7l9 21794 tr 1 21809 j809 to next routine 7 7 2 002 21796 + 4 2 002 21798 16 2 003 21801 231 2 001 21802 | 7 7 7 routine #232 7 test mpy and related adder 7 inputs. mpy 3 by 4. 7 21809 rad h 21866 j866 21814 mpy v 21867 j867 tn mc 2a, mc 2b. adder 21819 cmp 4 21869 j869 carry to get result of 12. 21824 tre l 21859 j859 7 21829 tra i 01 21859 j8v9 error routine 21834 sel 2 0500 21839 wr r 21870 j870 21844 tra i 03 21854 j8e4 21849 tr 1 21859 j859 21854 hlt j 0232 21859 tra i 02 21809 j8-9 21864 tr 1 21879 j879 7 2 002 21866 + 4 2 001 21867 +3 2 002 21869 12 2 003 21872 232 2 001 21873 | 7 7 7 routine #233 7 test mpy instruction on 7 a 2 digit multiplicand. 7 21879 rad h 21936 j936 21884 mpy v 21938 j938 mpy 11 by 1. 21889 cmp 4 21941 j941 21894 tre l 21929 j929 7 21899 tra i 01 21929 j9s9 error routine 21904 sel 2 0500 21909 wr r 21942 j942 21914 tra i 03 21924 j9b4 21919 tr 1 21929 j929 21924 hlt j 0233 21929 tra i 02 21879 j8p9 21934 tr 1 21954 j954 to next routine 7 7 2 002 21936 + 1 2 002 21938 +11 2 003 21941 011 2 003 21944 233 2 001 21945 | 7 7 routine #234 7 test mpy and related adder 7 inputs. mpy 15 by 4. 7 21954 rad h 22011 k011 21959 mpy v 22013 k013 tn and use mc 2a, mc 2b 21964 cmp 4 22016 k016 and doub. car. 21969 tre l 22004 k004 7 21974 tra i 01 22004 k0 4 error routine 21979 sel 2 0500 21984 wr r 22017 k017 21989 tra i 03 21999 j9i9 21994 tr 1 22004 k004 21999 hlt j 0234 22004 tra i 02 21954 j9n4 22009 tr 1 22029 k029 7 7 2 002 22011 + 4 2 002 22013 +15 2 003 22016 060 2 003 22019 234 2 001 22020 | 7 7 routine #235 7 test mpy and related adder 7 inputs. mpy 25 by 4. 7 22029 rad h 22086 k086 22034 mpy v 22088 k088 tn and use mc 2a, mc 2b 22039 cmp 4 22091 k091 and doub car. 22044 tre l 22079 k079 7 22049 tra i 01 22079 k0x9 error routine 22054 sel 2 0500 22059 wr r 22092 k092 22064 tra i 03 22074 k0g4 22069 tr 1 22079 k079 22074 hlt j 0235 22079 tra i 02 22029 k0k9 22084 tr 1 22104 k104 to next routine 7 7 2 002 22086 + 4 2 002 22088 +25 2 003 22091 100 2 003 22094 235 2 001 22095 | 7 7 7 routine #236 7 test mpy and related adder 7 inputs. mpy 45 by 4. 7 22104 rad h 22161 k161 22109 mpy v 22163 k163 tn and use mc 2a, mc 2b 22114 cmp 4 22166 k166 and doub car. 22119 tre l 22154 k154 7 22124 tra i 01 22154 k1v4 error routine 22129 sel 2 0500 22134 wr r 22167 k167 22139 tra i 03 22149 k1d9 22144 tr 1 22154 k154 22149 hlt j 0236 22154 tra i 02 22104 k1-4 22159 tr 1 22179 k179 7 7 2 002 22161 + 4 2 002 22163 +45 2 003 22166 180 2 003 22169 236 2 001 22170 | 7 routine #237 7 test mpy and related adder 7 inputs. mpy zero by 5. 7 22179 rad h 22231 k231 22184 mpy v 22232 k232 tn mc 5 to route sel 5 mpl 22189 trz n 22224 k224 when mbr equals zero. 7 22194 tra i 01 22224 k2s4 error routine 22199 sel 2 0500 22204 wr r 22233 k233 22209 tra i 03 22219 k2a9 22214 tr 1 22224 k224 22219 hlt j 0237 22224 tra i 02 22179 k1p9 22229 tr 1 22244 k244 to next routine 7 7 2 002 22231 + 5 2 001 22232 +0 2 003 22235 237 2 001 22236 | 7 7 7 routine #238 7 test mpy and related adder 7 inputs. mpy 1 by 5. 7 22244 rad h 22301 k301 22249 mpy v 22302 k302 tn mc 5 to route sle 5 mpl 22254 cmp 4 22304 k304 when mbr equals 1. 22259 tre l 22294 k294 7 22264 tra i 01 22294 k2z4 error routine 22269 sel 2 0500 22274 wr r 22305 k305 22279 tra i 03 22289 k2h9 22284 tr 1 22294 k294 22289 hlt j 0238 22294 tra i 02 22244 k2m4 22299 tr 1 22314 k314 7 7 2 002 22301 + 5 2 001 22302 +1 2 002 22304 05 2 003 22307 238 2 001 22308 | 7 7 7 routine #239 7 test mpy and related adder 7 inputs. mpy 2 by 5. 7 22314 rad h 22371 k371 22319 mpy v 22372 k372 tn and use mc 5, quin car 1 22324 cmp 4 22374 k374 while routing not mbr to ad. 22329 tre l 22364 k364 7 22334 tra i 01 22364 k3w4 error routine 22339 sel 2 0500 22344 wr r 22375 k375 22349 tra i 03 22359 k3e9 22354 tr 1 22364 k364 22359 hlt j 0239 22364 tra i 02 22314 k3j4 22369 tr 1 22384 k384 to next routine 7 7 2 002 22371 + 5 2 001 22372 +2 2 002 22374 10 2 003 22377 239 2 001 22378 | 7 7 7 routine #240 7 test mpy and related adder 7 inputs. mpy 4 by 5. 7 22384 rad h 22441 k441 22389 mpy v 22442 k442 tn and use mc 5, quin car 2 22394 cmp 4 22444 k444 while routing not mbr to ad. 22399 tre l 22434 k434 7 22404 tra i 01 22434 k4t4 error routine 22409 sel 2 0500 22414 wr r 22445 k445 22419 tra i 03 22429 k4b9 22424 tr 1 22434 k434 22429 hlt j 0240 22434 tra i 02 22384 k3q4 22439 tr 1 22454 k454 7 7 2 002 22441 + 5 2 001 22442 +4 2 002 22444 20 2 003 22447 240 2 001 22448 | 7 7 7 routine #241 7 test mpy and related adder 7 inputs. mpy 8 by 5. 7 22454 rad h 22511 k511 22459 mpy v 22512 k512 tn and use mc 5. quin car 4 22464 cmp 4 22514 k514 while routing not mbr to ad. 22469 tre l 22504 k504 7 22474 tra i 01 22504 k5 4 error routine 22479 sel 2 0500 22484 wr r 22515 k515 22489 tra i 03 22499 k4i9 22494 tr 1 22504 k504 22499 hlt j 0241 22504 tra i 02 22454 k4n4 22509 tr 1 22524 k524 to next routine 7 7 2 002 22511 + 5 2 001 22512 +8 2 002 22514 40 2 003 22517 241 2 001 22518 | 7 7 7 7 routine #242 7 test mpy and related adder 7 inputs. mpy 12 by 5. 7 22524 rad h 22581 k581 22529 mpy v 22583 k583 tn and use mc 5. quin car 2 22534 cmp 4 22586 k586 while mbr equals 1. 22539 tre l 22574 k574 7 22544 tra i 01 22574 k5X4 error routine 22549 sel 2 0500 22554 wr r 22587 k587 22559 tra i 03 22569 k5F9 22564 tr 1 22574 k574 22569 hlt j 0242 22574 tra i 02 22524 k5k4 22579 tr 1 22599 k599 7 7 2 002 22581 + 5 2 002 22583 +12 2 003 22586 060 2 003 22589 242 2 001 22590 | 7 7 7 routine #243 7 test mpy and related adder 7 inputs. mpy 16 by 5. 7 22599 rad h 22656 k656 22604 mpy v 22658 k658 tn and use mc 5. quin car 1 22609 cmp 4 22661 k661 quin car 2. when mbr is 1. 22614 tre l 22649 k649 7 22619 tra i 01 22649 k6u9 error routine 22624 sel 2 0500 22629 wr r 22662 k662 22634 tra i 03 22644 k6d4 22639 tr 1 22649 k649 22644 hlt j 0243 22649 tra i 02 22599 k5r9 22654 tr 1 22674 k674 to next routine 7 7 2 002 22656 + 5 2 002 22658 +16 2 003 22661 080 2 003 22664 243 2 001 22665 | 7 7 routine #244 7 test mpy and related adder 7 inputs. mpy 18 by 5. 7 22674 rad h 22731 k731 22679 mpy v 22733 k733 tn and use mc 5. quin car 4 22684 cmp 4 22736 k736 when mbr equals 1. 22689 tre l 22724 k724 7 22694 tra i 01 22724 k7s4 error routine 22699 sel 2 0500 22704 wr r 22737 k737 22709 tra i 03 22719 k7a9 22714 tr 1 22724 k724 22719 hlt j 0244 22724 tra i 02 22674 k6p4 22729 tr 1 22749 k749 7 2 002 22731 + 5 2 002 22733 +18 2 003 22736 090 2 003 22739 244 2 001 22740 | 7 7 routine #245 7 test mpy and related adder 7 inputs. mpy 1 by 3. 7 22749 rad h 22806 k806 22754 mpy v 22807 k807 tn mc 1 and mc 2a 22759 sub p 22806 k806 with mbr equal 1. 22764 trz n 22799 k799 7 22769 tra i 01 22799 k7z9 error routine 22774 sel 2 0500 22779 wr r 22808 k808 22784 tra i 03 22794 k7i4 22789 tr 1 22799 k799 22794 hlt j 0245 22799 tra i 02 22749 k7m9 22804 tr 1 22819 k819 to next routine 7 2 002 22806 + 3 2 001 22807 +1 2 003 22810 245 2 001 22811 | 7 7 7 7 routine #246 7 test mpy and related adder 7 inputs. mpy 1 by 6. 7 22819 rad h 22876 k876 22824 mpy v 22877 k877 tn mc 1 and mc 5 22829 sub p 22876 k876 with mbr equal 1. 22834 trz n 22869 k869 7 22839 tra i 01 22869 k8w9 error routine 22844 sel 2 0500 22849 wr r 22878 k878 22854 tra i 03 22864 k8f4 22859 tr 1 22869 k869 22864 hlt j 0246 22869 tra i 02 22819 k8j9 22874 tr 1 22889 k889 7 2 002 22876 + 6 2 001 22877 +1 2 003 22880 246 2 001 22881 | 7 7 7 routine #247 7 test mpy and related adder 7 inputs. mpy 1 by 7. 7 22889 rad h 22946 k946 22894 mpy v 22947 k947 tn mc 1 and mc 5 22899 sub p 22946 k946 with mbr equal 1. 22904 trz n 22939 k939 7 22909 tra i 01 22939 k9t9 error routine 22914 sel 2 0500 22919 wr r 22948 k948 22924 tra i 03 22934 k9c4 22929 tr 1 22939 k939 22934 hlt j 0247 22939 tra i 02 22889 k8q9 22944 tr 1 22959 k959 to next routine 7 2 002 22946 + 7 2 001 22947 +1 2 003 22950 247 2 001 22951 | 7 7 7 7 routine #248 7 test mpy and related adder 7 inputs. mpy 1 by 8. 7 22959 rad h 23016 l016 22964 mpy v 23017 l017 tn mc 1, 2b and mc 5 22969 sub p 23016 l016 with mbr equal 1. 22974 trz n 23009 l009 7 22979 tra i 01 23009 l0 9 error routine 22984 sel 2 0500 22989 wr r 23018 l018 22994 tra i 03 23004 l0+4 22999 tr 1 23009 l009 23004 hlt j 0248 23009 tra i 02 22959 k9n9 23014 tr 1 23029 l029 7 2 002 23016 + 8 2 001 23017 +1 2 003 23020 248 2 001 23021 | 7 7 7 routine #249 7 test mpy and related adder 7 inputs. mpy 1 by 9. 7 23029 rad h 23086 l086 23034 mpy v 23087 l087 tn mc 2a, mc 2b and mc 5 23039 sub p 23086 l086 with mbr equal 1. 23044 trz n 23079 l079 7 23049 tra i 01 23079 l0x9 error routine 23054 sel 2 0500 23059 wr r 23088 l088 23064 tra i 03 23074 l0g4 23069 tr 1 23079 l079 23074 hlt j 0249 23079 tra i 02 23029 l0k9 23084 tr 1 23099 l099 to next routine 7 2 002 23086 + 9 2 001 23087 +1 2 003 23090 249 2 001 23091 | 7 7 7 routine #250 7 test mpy and related adder 7 inputs. mpy 2 by 8. 7 23099 rad h 23156 l156 23104 mpy v 23157 l157 tn mc 1, mc 2b and mc 5 23109 cmp 4 23159 l159 with mbr equal 2. 23114 tre l 23149 l149 7 23119 tra i 01 23149 l1u9 error routine 23124 sel 2 0500 23129 wr r 23160 l160 23134 tra i 03 23144 l1d4 23139 tr 1 23149 l149 23144 hlt j 0250 23149 tra i 02 23099 l0r9 23154 tr 1 23169 l169 7 7 2 002 23156 + 8 2 001 23157 +2 2 002 23159 16 2 003 23162 250 2 001 23163 | 7 7 routine #251 7 test mpy and related adder 7 inputs. mpy 3 by 8. 7 23169 rad h 23226 l226 23174 mpy v 23227 l227 tn mc 1, mc 2b and mc 5 23179 cmp 4 23229 l229 with mbr equal 3. 23184 tre l 23219 l219 7 23189 tra i 01 23219 l2/9 error routine 23194 sel 2 0500 23199 wr r 23230 l230 23204 tra i 03 23214 l2a4 23209 tr 1 23219 l219 23214 hlt j 0251 23219 tra i 02 23169 l1o9 23224 tr 1 23239 l239 7 7 2 002 23226 + 8 2 001 23227 +3 2 002 23229 24 2 003 23232 251 2 001 23233 | 7 7 routine #252 7 test mpy and related adder 7 inputs. mpy 9 by 3. 7 23239 rad h 23296 l296 23244 mpy v 23297 l297 tn and use mc 1, mc 2a 23249 cmp 4 23299 l299 with doub car. 23254 tre l 23289 l289 7 23259 tra i 01 23289 l2y9 error routine 23264 sel 2 0500 23269 wr r 23300 l300 23274 tra i 03 23284 l2h4 23279 tr 1 23289 l289 23284 hlt j 0252 23289 tra i 02 23239 l2l9 23294 tr 1 23309 l309 7 7 2 002 23296 + 3 2 001 23297 +9 2 002 23299 27 2 003 23302 252 2 001 23303 | 7 7 routine #253 7 test mpy and related adder 7 inputs. mpy 6 by 7. 7 23309 rad h 23366 l366 23314 mpy v 23367 l367 use mc 2a, mc5, doub car, 23319 cmp 4 23369 l369 quin car 1 and quin car 2. 23324 tre l 23359 l359 7 23329 tra i 01 23359 l3v9 error routine 23334 sel 2 0500 23339 wr r 23370 l370 23344 tra i 03 23354 l3e4 23349 tr 1 23359 l359 23354 hlt j 0253 23359 tra i 02 23309 l3-9 23364 tr 1 23379 l379 7 7 2 002 23366 + 7 2 001 23367 +6 2 002 23369 42 2 003 23372 253 2 001 23373 | 7 7 routine #254 7 test mpy and related adder 7 inputs. mpy 6 by 3. 7 23379 rad h 23436 l436 23384 mpy v 23437 l437 tn and use mc 1, mc 2a. 23389 cmp 4 23439 l439 and doub car. 23394 tre l 23429 l429 7 23399 tra i 01 23429 l4s9 error routine 23404 sel 2 0500 23409 wr r 23440 l440 23414 tra i 03 23424 l4b4 23419 tr 1 23429 l429 23424 hlt j 0254 23429 tra i 02 23379 l3p9 23434 tr 1 23449 l449 7 7 2 002 23436 + 3 2 001 23437 +6 2 002 23439 18 2 003 23442 254 2 001 23443 | 7 7 7 routine #255 7 test mpy and related adder 7 inputs. mpy 4 by 8. 7 23449 rad h 23506 l506 23454 mpy v 23507 l507 tn and use mc 1, mc 2b, 23459 cmp 4 23509 l509 mc 5 and quin car 2. 23464 tre l 23499 l499 7 23469 tra i 01 23499 l4z9 error routine 23474 sel 2 0500 23479 wr r 23510 l510 23484 tra i 03 23494 l4i4 23489 tr 1 23499 l499 23494 hlt j 0255 23499 tra i 02 23449 l4m9 23504 tr 1 23519 l519 to next routine 7 7 2 002 23506 + 8 2 001 23507 +4 2 002 23509 32 2 003 23512 255 2 001 23513 | 7 7 7 routine #256 7 test mpy and related adder 7 inputs. mpy 8 by 8. 7 23519 rad h 23576 l576 23524 mpy v 23576 l576 tn and use mc 1, mc 2b, mc 5 23529 cmp 4 23578 l578 doub car and quin car 4. 23534 tre l 23569 l569 7 23539 tra i 01 23569 l5w9 error routine 23544 sel 2 0500 23549 wr r 23579 l579 23554 tra i 03 23564 l5f4 23559 tr 1 23569 l569 23564 hlt j 0256 23569 tra i 02 23519 l5j9 23574 tr 1 23589 l589 7 7 2 002 23576 + 8 2 002 23578 64 2 003 23581 256 2 001 23582 | 7 7 7 7 routine #257 7 test mpy instruction on 7 a 2 digit multiplier. 7 23589 rad h 23647 l647 23594 mpy v 23648 l648 mpy 1 by 11. 23599 cmp 4 23651 l651 23604 tre l 23639 l639 7 23609 tra i 01 23639 l6t9 error routine 23614 sel 2 0500 23619 wr r 23652 l652 23624 tra i 03 23634 l6c4 23629 tr 1 23639 l639 23634 hlt j 0257 23639 tra i 02 23589 l5q9 23644 tr 1 23664 l664 to next routinE 7 7 2 003 23647 + 11 2 001 23648 +1 2 003 23651 011 2 003 23654 257 2 001 23655 | 7 7 7 routine #258 7 test mpy instruction 7 mpy 11 by 11. 7 23664 rad h 23722 l722 23669 mpy v 23722 l722 23674 cmp 4 23726 l726 23679 tre l 23714 l714 7 23684 tra i 01 23714 l7/4 error routine 23689 sel 2 0500 23694 wr r 23727 l727 23699 tra i 03 23709 l7+9 23704 tr 1 23714 l714 23709 hlt j 0258 23714 tra i 02 23664 l6o4 23719 tr 1 23739 l739 7 7 2 003 23722 + 11 2 004 23726 0121 2 003 23729 258 2 001 23730 | 7 7 7 routine #259 7 test mpy instruction 7 mpy 78 by 78. 7 23739 rad h 23797 l797 23744 mpy v 23797 l797 23749 sub p 23801 l801 23754 trz n 23789 l789 7 23759 tra i 01 23789 l7y9 error routine 23764 sel 2 0500 23769 wr r 23802 l802 23774 tra i 03 23784 l7h4 23779 tr 1 23789 l789 23784 hlt j 0259 23789 tra i 02 23739 l7l9 23794 tr 1 23814 l814 to next routinE 7 7 2 003 23797 + 78 2 004 23801 +6084 2 003 23804 259 2 001 23805 | 7 7 routine #260 7 test mpy instruction 7 23814 rad h 23885 l885 jumbo multiply 23819 mpy v 23885 l885 9876543210 x 9876543210 23824 set b 0020 ans. 97546105778997104100 23829 cmp 4 23905 l905 23834 tre l 23869 l869 7 23839 tra i 01 23869 l8w9 error routine 23844 sel 2 0500 23849 wr r 23906 l906 23854 tra i 03 23864 l8f4 23859 tr 1 23869 l869 23864 hlt j 0260 23869 tra i 02 23814 l8j4 23874 tr 1 23914 l914 7 7 2 011 23885 + 9876543210 2 020 23905 97546105778997104100 2 003 23908 260 2 001 23909 | 7 7 7 routine #261 7 test mpy. verify 7 multiplier after doing mpy. 7 23914 rad h 23987 l987 23919 mpy v 23987 l987 mpy 11 by 11 23924 shr c 0128 23929 sub p 23987 l987 23934 trz n 23969 l969 7 23939 tra i 01 23969 l9w9 error routine 23944 sel 2 0500 23949 wr r 23988 l988 23954 tra i 03 23964 l9f4 23959 tr 1 23969 l969 23964 hlt j 0261 23969 tra i 02 23914 l9j4 23974 rcv u 0306 23979 tr 1 01 0204 02 4 23984 tr 1 23999 l999 to next routine 7 7 2 003 23987 + 11 2 003 23990 261 2 001 23991 | 7 7 7 7 7 routine #262 7 execute div tc 1, 2, 3 only. 7 test for no 900 check 7 test for tn dzt in tc-1. 7 23999 eem 3 14 0000 0+-0 24004 spc , 0001 24009 set b 0000 place storage mark 24014 rad h 01 24071 m0x1 turn off dzt 24019 div w 24071 m071 do divide 24024 trs o 10 24034 m-l4 24029 trz n 24064 m064 7 24034 tra i 01 24064 m0w4 error routine 24039 sel 2 0500 24044 wr r 24072 m072 24049 tra i 03 24059 m0e9 24054 tr 1 24064 m064 24059 hlt j 0262 24064 tra i 02 23999 l9r9 24069 tr 1 24084 m084 7 7 2 002 24071 A 2 003 24074 262 2 001 24075 | 7 7 7 routine #263 7 test div. do tc 1, 2, 3 only. 7 test for stor mark placed at 7 right of dividend in tc 1 7 24084 eem 3 14 0000 0+-0 24089 spc , 0001 24094 rad h 24185 m185 rad 123 to preset storage 24099 set b 0000 dividend is a storage mark 24104 div w 24181 m181 24109 spc , 0002 spc to 12 and check that 24114 cmp 4 24184 m184 area to left of dividend 24119 tre l 24129 m129 is unchanged 24124 tr 1 24144 m144 24129 spc , 0000 spc to stor mark placed 24134 cmp 4 24189 m189 by tc 2 and cmp vs group 24139 tre l 24174 m174 mark-should be equal. 7 24144 tra i 01 24174 m1x4 error routine 24149 sel 2 0500 24154 wr r 24186 m186 24159 tra i 03 24169 m1f9 24164 tr 1 24174 m174 24169 hlt j 0263 24174 tra i 02 24084 m0q4 24179 tr 1 24194 m194 to next routine 7 2 002 24181 + 1 2 004 24185 + 123 2 003 24188 263 2 001 24189 | 7 7 7 routine #264 7 test div. do tc 1, 2, 3 only. 7 test for stor mark placed at 7 left of quotient area in tc 2 7 24194 eem 3 14 0000 0+-0 24199 spc , 0401 24204 rad h 24300 m300 preset quotient area to 123 24209 spc , 0001 24214 set b 0000 dividend is a storage mark 24219 div w 24296 m296 24224 shr c 0128 shr to quotient storage 24229 cmp 4 24304 m304 mark and cmp vs group mark. 24234 tre l 24244 m244 should be equal. 24239 tr 1 24259 m259 24244 shr c 0001 step over quot. stor mark 24249 cmp 4 24299 m299 and cmp vs 12 24254 tre l 24289 m289 7 24259 tra i 01 24289 m2y9 error routine 24264 sel 2 0500 24269 wr r 24301 m301 24274 tra i 03 24284 m2h4 24279 tr 1 24289 m289 24284 hlt j 0264 24289 tra i 02 24194 m1r4 24294 tr 1 24309 m309 to next routine 7 2 002 24296 + 1 2 004 24300 + 123 2 003 24303 264 2 001 24304 | 7 7 routine #265 7 test div. do tc 1, 2, 3 only. 7 tn aux 1 to rd storage in tc-2 7 div +000 by +000. 7 24309 eem 3 14 0000 0+-0 24314 spc , 0736 spc to char. 6 24319 rad h 24391 m391 dividend is 000 24324 div w 24391 m391 24329 cmp 4 24395 m395 test dividend not a storage 24334 tre l 24349 m349 mark and 24339 cmp 4 24387 m387 equal to 000. 24344 tre l 24379 m379 7 24349 tra i 01 24379 m3x9 error routine 24354 sel 2 0500 24359 wr r 24392 m392 24364 tra i 03 24374 m3g4 24369 tr 1 24379 m379 24374 hlt j 0265 24379 tra i 02 24309 m3-9 24384 tr 1 24404 m404 7 2 003 24387 000 2 004 24391 + 000 2 003 24394 265 2 001 24395 | 7 7 routine #266 7 test div. 00 by 0. do type 7 cycles 1,2,3,4,5,5,4-end op. 7 check for quotient of 1, and 7 dzt off. 7 24404 eem 3 14 0000 0+-0 24409 spc , 0001 24414 rad h 24488 m488 even division first tc 4. 24419 div w 24486 m486 in tc 5-tf dzt. result 1 to 24424 trz n 24449 m449 quot., step spc - 1. 24429 cmp 4 24493 m493 24434 tre l 24449 m449 test quotient for not a stor 24439 cmp 4 24489 m489 mark and equal 1. 24444 tre l 24479 m479 7 24449 tra i 01 24479 m4x9 error routine 24454 sel 2 0500 24459 wr r 24490 m490 24464 tra i 03 24474 m4g4 24469 tr 1 24479 m479 24474 hlt j 0266 24479 tra i 02 24404 m4-4 24484 tr 1 24499 m499 to next routine 7 2 002 24486 + 0 2 002 24488 +00 2 001 24489 1 2 003 24492 266 2 001 24493 | 7 7 7 routine #267 7 test div for set storage 7 sign minus in end of tc 4. 7 div again and set sign plus. 7 24499 rad h 24567 m567 00 24504 div w 24569 m569 div +00 by -0. 24509 trp m 24529 m529 test not plus 24514 rad h 24567 m567 24519 div w 24571 m571 div +00 by +0. 24524 trp m 24559 m559 test plus 7 24529 tra i 01 24559 m5v9 error routine 24534 sel 2 0500 24539 wr r 24572 m572 24544 tra i 03 24554 m5e4 24549 tr 1 24559 m559 24554 hlt j 0267 24559 tra i 02 24499 m4r9 24564 tr 1 24584 m584 7 2 003 24567 + 00 2 002 24569 - 0 2 002 24571 + 0 2 003 24574 267 2 001 24575 | 7 7 7 routine #268 7 test divide tc 4 and 5 7 variations. divide 00 by 1. 7 do tc 1,2,3,4,5,4,5,4-end op. 7 24584 eem 3 14 0000 0+-0 24589 spc , 0001 24594 rad h 24663 m663 00 24599 div w 24661 m661 result a zero to quotient. 24604 cmp 4 24662 m662 24609 tre l 24619 m619 24614 tr 1 24624 m624 24619 trz n 24654 m654 test dzt on. 7 24624 tra i 01 24654 m6v4 error routine 24629 sel 2 0500 24634 wr r 24664 m664 24639 tra i 03 24649 m6d9 24644 tr 1 24654 m654 24649 hlt j 0268 24654 tra i 02 24584 m5q4 24659 tr 1 24674 m674 to next routine 7 2 002 24661 A 2 002 24663 +00 2 003 24666 268 2 001 24667 | 7 7 7 7 routine #269 7 test divide tc 4 for set 7 sign plus when dzt on. 7 divide +00 by -1. 7 24674 rad h 24727 m727 24679 div w 24729 m729 dzt on-set sign plus 24684 trp m 24719 m719 7 24689 tra i 01 24719 m7/9 error routine 24694 sel 2 0500 24699 wr r 24730 m730 24704 tra i 03 24714 m7a4 24709 tr 1 24719 m719 24714 hlt j 0269 24719 tra i 02 24674 m6p4 24724 tr 1 24739 m739 7 2 003 24727 + 00 2 002 24729 - 1 2 003 24732 269 2 001 24733 | 7 7 7 7 7 routine #270 7 test divide tc 4 and 5 7 variations. div 10 by 5. 7 do tc 1,2,3,4-5,4-5,4-end op. 7 24739 eem 3 14 0000 0+-0 24744 spc , 0001 24749 rad h 24807 m807 10 24754 div w 24809 m809 24759 cmp 4 24810 m810 check quotient equal 2. 24764 tre l 24799 m799 7 24769 tra i 01 24799 m7z9 error routine 24774 sel 2 0500 24779 wr r 24811 m811 24784 tra i 03 24794 m7i4 24789 tr 1 24799 m799 24794 hlt j 0270 24799 tra i 02 24739 m7l9 24804 tr 1 24819 m819 to next routine 7 2 003 24807 + 10 2 002 24809 + 5 2 001 24810 2 2 003 24813 270 2 001 24814 | 7 7 7 routine #271 7 test divide tc 4 and 5 7 variations. div 19 by 8. 7 check quot. 2 and rem. 03. 7 24819 eem 3 14 0000 0+-0 24824 spc , 0001 24829 rad h 24907 m907 19 24834 div w 24909 m909 24839 cmp 4 24910 m910 cmp quotient 24844 tre l 24854 m854 24849 tr 1 24869 m869 24854 spc , 0001 spc to remainder and 24859 cmp 4 24912 m912 cmp for 03. 24864 tre l 24899 m899 7 24869 tra i 01 24899 m8z9 error routine 24874 sel 2 0500 24879 wr r 24913 m913 24884 tra i 03 24894 m8i4 24889 tr 1 24899 m899 24894 hlt j 0271 24899 tra i 02 24819 m8j9 24904 tr 1 24924 m924 7 2 003 24907 + 19 2 002 24909 + 8 2 001 24910 2 2 002 24912 03 2 003 24915 271 2 001 24916 | 7 7 7 routine #272 7 test divide 15 by 2 7 check quot. and remainder. 7 24924 rad h 25003 n003 rad 15 24929 div w 25001 n001 24934 cmp 4 25004 n004 check quotient 7 24939 tre l 24949 m949 24944 tr 1 24964 m964 24949 shr c 0127 shr to remainder 24954 cmp 4 25006 n006 and cmp vs 01. 24959 tre l 24994 m994 7 24964 tra i 01 24994 m9z4 error routine 24969 sel 2 0500 24974 wr r 25007 n007 24979 tra i 03 24989 m9h9 24984 tr 1 24994 m994 24989 hlt j 0272 24994 tra i 02 24924 m9k4 24999 tr 1 25019 n019 to next routine 7 2 002 25001 + 2 2 002 25003 +15 2 001 25004 7 2 002 25006 01 2 003 25009 272 2 001 25010 | 7 7 7 routine #273 7 test divide 032 by 3 7 check quot. and remainder. 7 25019 rad h 25099 n099 25024 div w 25096 n096 25029 cmp 4 25101 n101 cmp quotient of 10 25034 tre l 25044 n044 25039 tr 1 25059 n059 25044 shr c 0127 shr to remainder 25049 cmp 4 25104 n104 and cmp vs 002 25054 tre l 25089 n089 7 25059 tra i 01 25089 n0y9 error routine 25064 sel 2 0500 25069 wr r 25105 n105 25074 tra i 03 25084 n0h4 25079 tr 1 25089 n089 25084 hlt j 0273 25089 tra i 02 25019 n0j9 25094 tr 1 25114 n114 7 2 002 25096 + 3 2 003 25099 +032 2 002 25101 10 2 003 25104 002 2 003 25107 273 2 001 25108 | 7 7 7 routine #274 7 test divide -09825 by -25. 7 check quotient of 393 and 7 remainder of 00000. 7 test sign plus. 7 25114 rad h 25202 n202 25119 div w 25197 n197 25124 cmp 4 25205 n205 check quotient 25129 tre l 25139 n139 25134 tr 1 25159 n159 25139 trp m 25149 n149 25144 tr 1 25159 n159 25149 shr c 0126 shr to remainder 25154 trz n 25189 n189 and test zeros 7 25159 tra i 01 25189 n1y9 error routine 25164 sel 2 0500 25169 wr r 25206 n206 25174 tra i 03 25184 n1h4 25179 tr 1 25189 n189 25184 hlt j 0274 25189 tra i 02 25114 n1j4 25194 tr 1 25214 n214 to next routine 7 2 003 25197 - 25 2 005 25202 -09825 2 003 25205 393 2 003 25208 274 2 001 25209 | 7 7 7 routine #275 7 test divide +1234 by -98. 7 check quotient of 12, 7 remainder of 0058 and 7 sign minus. 7 25214 rad h 25301 n301 25219 div w 25297 n297 25224 cmp 4 25303 n303 check quotient of 12 25229 tre l 25239 n239 25234 tr 1 25259 n259 25239 trp m 25259 n259 check sign minus 25244 shr c 0126 shr to remainder 25249 cmp 4 25307 n307 and cmp vs 0058 25254 tre l 25289 n289 7 25259 tra i 01 25289 n2y9 error routine 25264 sel 2 0500 25269 wr r 25308 n308 25274 tra i 03 25284 n2h4 25279 tr 1 25289 n289 25284 hlt j 0275 25289 tra i 02 25214 n2j4 25294 tr 1 25319 n319 7 2 003 25297 - 98 2 004 25301 +1234 2 002 25303 12 2 004 25307 0058 2 003 25310 275 2 001 25311 | 7 7 7 routine #276 7 test divide instruction 7 25319 rad h 25435 n435 jumbo divide 25324 div w 25445 n445 97546105779984758421 25329 set b 0010 divided by 9876543210 25334 cmp 4 25455 n455 ans. 9876543210 plus a 25339 tre l 25349 n349 rmdr of 0987654321 25344 tr 1 25369 n369 25349 shr c 0118 25354 set b 0010 25359 cmp 4 25465 n465 25364 tre l 25399 n399 7 25369 tra i 01 25399 n3z9 error routine 25374 sel 2 0500 25379 wr r 25466 n466 25384 tra i 03 25394 n3i4 25389 tr 1 25399 n399 25394 hlt j 0276 25399 tra i 02 25319 n3j9 25404 rcv u 0306 25409 tr 1 01 0204 02 4 25414 tr 1 25474 n474 to next routine 7 2 021 25435 + 97546105779984758421 2 010 25445 +9876543210 2 010 25455 9876543210 2 010 25465 0987654321 2 003 25468 276 2 001 25469 | 7 7 routine #277 7 test of lda instruction 7 for execution + no 7 op check 7 25474 set b 0005 25479 lda = 25534 n534 test instruction 25484 trs o 10 25494 nmr4 25489 trp m 25524 n524 7 25494 tra i 01 25524 n5s4 error routine 25499 sel 2 0500 25504 wr r 25535 n535 25509 tra i 03 25519 n5a9 25514 tr 1 25524 n524 25519 hlt j 0277 25524 tra i 02 25474 n4p4 25529 tr 1 25544 n544 7 2 005 25534 9684 2 003 25537 277 2 001 25538 | 7 7 routine #278 7 test lda in 7080 mode. 7 lda 9876 and test 7 storage result of 009876. 7 25544 eem 3 14 0000 0+-0 25549 set b 0005 reset storage 25554 lod 8 25629 n629 25559 lda = 25634 n634 25564 unl 7 25640 n640 25569 set b 0006 25574 lod 8 25646 n646 25579 cmp 4 25640 n640 check result 25584 tre l 25619 n619 7 25589 tra i 01 25619 n6/9 error routine 25594 sel 2 0500 25599 wr r 25647 n647 25604 tra i 03 25614 n6a4 25609 tr 1 25619 n619 25614 hlt j 0278 25619 tra i 02 25544 n5m4 25624 tr 1 25659 n659 7 2 005 25629 +++++ 2 005 25634 9876 2 006 25640 2 006 25646 009876 2 003 25649 278 2 001 25650 | 7 7 routine #279 7 test lda in 7080 mode. 7 lda edcb and test 7 storage result of 155432. 7 25659 eem 3 14 0000 0+-0 25664 set b 0003 reset storage 25669 lod 8 25749 n749 25674 lda = 25744 n744 25679 unl 7 25755 n755 25684 set b 0006 25689 lod 8 25761 n761 25694 cmp 4 25755 n755 check result 25699 tre l 25734 n734 7 25704 tra i 01 25734 n7t4 error routine 25709 sel 2 0500 25714 wr r 25762 n762 25719 tra i 03 25729 n7b9 25724 tr 1 25734 n734 25729 hlt j 0279 25734 tra i 02 25659 n6n9 25739 tr 1 25774 n774 7 2 005 25744 edcb 2 005 25749 0348 2 006 25755 2 006 25761 155432 2 003 25764 279 2 001 25765 | 7 7 routine #280 7 test lda instruction with 7 address of zero to check 7 that dzt comes on. 7 25774 eem 3 14 0000 0+-0 7080 mode 25779 set b 0006 25784 lod 8 25840 n840 25789 lda = 25844 n844 memory field zero 25794 trz n 25829 n829 7 25799 tra i 01 25829 n8s9 error routine 25804 sel 2 0500 25809 wr r 25845 n845 25814 tra i 03 25824 n8b4 25819 tr 1 25829 n829 25824 hlt j 0280 25829 tra i 02 25774 n7p4 25834 tr 1 25854 n854 to next routine 7 2 006 25840 155432 2 004 25844 0000 2 003 25847 280 2 001 25848 | 7 7 25854 lem 3 15 0000 0++0 routine #281 25859 set b 0007 test lda instrcution 25864 lod 8 25946 n946 on non-zero address. 25869 lda = 25954 n954 check for tf dzt. 25874 unl 7 25961 n961 25879 trz n 25904 n904 dzt on error 25884 set b 0005 25889 lod 8 25966 n966 25894 cmp 4 25961 n961 check storage 25899 tre l 25934 n934 7 25904 tra i 01 25934 n9t4 error routine 25909 sel 2 0500 25914 wr r 25967 n967 25919 tra i 03 25929 n9b9 25924 tr 1 25934 n934 25929 hlt j 0281 25934 tra i 02 25854 n8n4 25939 tr 1 25979 n979 7 2 007 25946 1100000 2 008 25954 00001 2 007 25961 2 005 25966 00001 2 003 25969 281 2 001 25970 | 7 7 routine #282 7 test lda in 705-3 mode. 7 lda on aaaa and test 7 for storage result of 71111 7 25979 lem 3 15 0000 0++0 25984 set b 0004 reset storage 25989 lod 8 26074 o074 25994 lda = 26079 o079 25999 set b 0005 26004 unl 7 26084 o084 26009 lod 8 26089 o089 26014 cmp 4 26084 o084 check storage 26019 tre l 26054 o054 7 26024 tra i 01 26054 o0v4 error routine 26029 sel 2 0500 26034 wr r 26090 o090 26039 tra i 03 26049 o0d9 26044 tr 1 26054 o054 26049 hlt j 0282 26054 tra i 02 25979 n9p9 26059 rcv u 0306 26064 tr 1 01 0204 02 4 26069 tr 1 26099 o099 to next routine 7 2 005 26074 44444 2 005 26079 aaaa 2 005 26084 2 005 26089 71111 2 003 26092 282 2 001 26093 | 7 7 routine #283 7 test ula for execution. 7 + no op check 7 26099 set b 0000 26104 set b 0005 26109 ula * 26164 o164 26114 trs o 10 26124 ojk4 26119 tr 1 26154 o154 7 26124 tra i 01 26154 o1v4 error routine 26129 sel 2 0500 26134 wr r 26165 o165 26139 tra i 03 26149 o1d9 26144 tr 1 26154 o154 26149 hlt j 0283 26154 tra i 02 26099 o0r9 26159 tr 1 26174 o174 7 2 005 26164 2 003 26167 283 2 001 26168 | 7 7 routine #284 7 test ula in 7080 mode 7 ula 360000 and test 7 result of 0000 in memory 7 26174 eem 3 14 0000 0+-0 26179 set b 0006 26184 lod 8 26270 o270 26189 set b 01 0004 00 4 26194 lod 8 01 26278 o2x8 26199 unl 7 01 26274 o2x4 26204 ula * 26274 o274 26209 set b 0004 26214 lod 8 26282 o282 26219 cmp 4 26274 o274 26224 tre l 26259 o259 7 26229 tra i 01 26259 o2v9 error routine 26234 sel 2 0500 26239 wr r 26283 o283 26244 tra i 03 26254 o2e4 26249 tr 1 26259 o259 26254 hlt j 0284 26259 tra i 02 26174 o1p4 26264 tr 1 26294 o294 to next routine 7 2 006 26270 360000 2 004 26274 2 004 26278 5326 2 004 26282 0000 2 003 26285 284 2 001 26286 | 7 7 routine #285 7 test ula in 7080 mode 7 ula 076543 into memory 7 field containing asu zones. 7 26294 eem 3 14 0000 0+-0 26299 set b 0006 26304 lod 8 26390 o390 storage field for ula 26309 set b 01 0004 00 4 26314 lod 8 01 26398 o3z8 26319 unl 7 01 26394 o3z4 reset memory field 26324 ula * 26394 o394 26329 set b 0004 26334 lod 8 26402 o402 26339 cmp 4 26394 o394 26344 tre l 26379 o379 7 26349 tra i 01 26379 o3x9 error routine 26354 sel 2 0500 26359 wr r 26403 o403 26364 tra i 03 26374 o3g4 26369 tr 1 26379 o379 26374 hlt j 0285 26379 tra i 02 26294 o2r4 26384 tr 1 26414 o414 7 2 006 26390 076543 2 004 26394 2 004 26398 0bcz 2 004 26402 fedl 2 003 26405 285 2 001 26406 | 7 7 26414 eem 3 14 0000 0+-0 routine #286 26419 set b 0006 test ula in 7080 mode 26424 lod 8 26510 o510 ula 126813 and test 26429 set b 01 0004 00 4 memory result of 681c 26434 lod 8 01 26518 o5/8 26439 unl 7 01 26514 o5/4 reset memory field 26444 ula * 26514 o514 zones in storage on ula 26449 set b 0004 26454 lod 8 26522 o522 26459 cmp 4 26514 o514 26464 tre l 26499 o499 7 26469 tra i 01 26499 o4z9 error routine 26474 sel 2 0500 26479 wr r 26523 o523 26484 tra i 03 26494 o4i4 26489 tr 1 26499 o499 26494 hlt j 0286 26499 tra i 02 26414 o4j4 26504 tr 1 26534 o534 to next routine 7 2 006 26510 12fha3 2 004 26514 2 004 26518 r999 2 004 26522 681c 2 003 26525 286 2 001 26526 | 7 7 routine #287 7 test ula with a 7 storage length of 7 4 in 7080 mode 7 26534 eem 3 14 0000 0+-0 26539 set b 0004 26544 lod 8 26630 o630 storage field for ula 26549 set b 01 0004 00 4 26554 lod 8 01 26638 o6t8 26559 unl 7 01 26634 o6t4 reset memory field 26564 ula * 26634 o634 26569 set b 0004 26574 lod 8 26642 o642 26579 cmp 4 26634 o634 26584 tre l 26619 o619 7 26589 tra i 01 26619 o6/9 error routine 26594 sel 2 0500 26599 wr r 26643 o643 26604 tra i 03 26614 o6a4 26609 tr 1 26619 o619 26614 hlt j 0287 26619 tra i 02 26534 o5l4 26624 tr 1 26654 o654 7 2 006 26630 145682 2 004 26634 2 004 26638 i99i 2 004 26642 5682 2 003 26645 287 2 001 26646 | 7 7 26654 lem 3 15 0000 0++0 routine #288 26659 set b 0006 test ula in 705-3 mode 26664 lod 8 26750 o750 with storage length 26669 set b 01 0004 00 4 of six. 26674 lod 8 01 26758 o7v8 26679 unl 7 01 26754 o7v4 reset memory field 26684 ula * 26754 o754 26689 set b 0004 26694 lod 8 26762 o762 26699 cmp 4 26754 o754 26704 tre l 26739 o739 7 26709 tra i 01 26739 o7t9 error routine 26714 sel 2 0500 26719 wr r 26763 o763 26724 tra i 03 26734 o7c4 26729 tr 1 26739 o739 26734 hlt j 0288 26739 tra i 02 26654 o6n4 26744 tr 1 26774 o774 to next routine 7 2 006 26750 159999 2 004 26754 2 004 26758 j11/ 2 004 26762 z99I 2 003 26765 288 2 001 26766 | 7 7 routine #289 7 test of ula for wrap 7 around at 80k in 7 705 iii mode. 7 26774 lem 3 15 0000 0++0 26779 set b 0006 26784 lod 8 26870 o870 storage field for ula 26789 set b 01 0004 00 4 26794 lod 8 01 26878 o8x8 26799 unl 7 01 26874 o8x4 reset memory field 26804 ula * 26874 o874 26809 set b 0004 26814 lod 8 26882 o882 26819 cmp 4 26874 o874 26824 tre l 26859 o859 7 26829 tra i 01 26859 o8v9 error routine 26834 sel 2 0500 26839 wr r 26883 o883 26844 tra i 03 26854 o8e4 26849 tr 1 26859 o859 26854 hlt j 0289 26859 tra i 02 26774 o7p4 26864 tr 1 26894 o894 7 2 006 26870 180000 2 004 26874 2 004 26878 dll0 2 004 26882 0--0 2 003 26885 289 2 001 26886 | 7 7 26894 lem 3 15 0000 0++0 routine #290 26899 set b 0003 test ula in 705-3 mode 26904 lod 8 27000 p000 with storage length 26909 set b 01 0004 00 4 of three. 26914 lod 8 01 27008 p0 8 26919 unl 7 01 27004 p0 4 reset memory field 26924 ula * 27004 p004 26929 set b 0004 26934 lod 8 27012 p012 26939 cmp 4 27004 p004 26944 tre l 26979 o979 7 26949 tra i 01 26979 o9x9 error routine 26954 sel 2 0500 26959 wr r 27013 p013 26964 tra i 03 26974 o9g4 26969 tr 1 26979 o979 26974 hlt j 0290 26979 tra i 02 26894 o8r4 26984 rcv u 0306 26989 tr 1 01 0204 02 4 26994 tr 1 27024 p024 to next routine 7 2 006 27000 132456 2 004 27004 2 004 27008 a65m 2 004 27012 0456 2 003 27015 290 2 001 27016 | 7 7 routine #291 7 test aam for execution 7 + no op check 7 27024 set b 0000 27029 set b 0005 put zeros in storage 27034 aam @ 27089 p089 27039 trs o 10 27049 p-m9 27044 tr 1 27079 p079 7 27049 tra i 01 27079 p0x9 error routine 27054 sel 2 0500 27059 wr r 27090 p090 27064 tra i 03 27074 p0g4 27069 tr 1 27079 p079 27074 hlt j 0290 27079 tra i 02 27024 p0k4 27084 tr 1 27099 p099 7 2 005 27089 9999 2 003 27092 291 2 001 27093 | 7 7 7 routine #292 7 test aam in 7080 mode. 7 with storage field of 7 six zeros. 7 27099 eem 3 14 0000 0+-0 27104 set b 0006 27109 lod 8 27205 p205 put plus zeros in acc. 27114 set b 01 0004 00 4 27119 lod 8 01 27213 p2/3 27124 unl 7 01 27209 p2 9 reset memory field 27129 aam @ 27209 p209 27134 cmp 4 27219 p219 test storage unchanged 27139 tre l 27149 p149 27144 tr 1 27164 p164 27149 lod 8 01 27213 p2/3 27154 cmp 4 01 27209 p2 9 test memory result 27159 tre l 27194 p194 7 27164 tra i 01 27194 p1z4 error routine 27169 sel 2 0500 27174 wr r 27220 p220 27179 tra i 03 27189 p1h9 27184 tr 1 27194 p194 27189 hlt j 0292 27194 tra i 02 27099 p0r9 27199 tr 1 27229 p229 to next routine 7 2 006 27205 +++00+ 2 004 27209 2 004 27213 5555 2 006 27219 +++00+ 2 003 27222 292 2 001 27223 | 7 7 7 routine #293 7 test aam in 7080 mode. 7 with zones in both storage 7 + memory. 7080 mode 7 27229 eem 3 14 0000 0+-0 27234 set b 0006 27239 lod 8 27325 p325 lod storage with adbbcd 27244 set b 01 0004 00 4 27249 lod 8 01 27333 p3t3 27254 unl 7 01 27329 p3s9 reset memory with wqqb 27259 aam @ 27329 p329 adm result equal ij/u 27264 set b 0004 27269 lod 8 27337 p337 27274 cmp 4 27329 p329 27279 tre l 27314 p314 7 27284 tra i 01 27314 p3/4 error routine 27289 sel 2 0500 27294 wr r 27338 p338 27299 tra i 03 27309 p3+9 27304 tr 1 27314 p314 27309 hlt j 0293 27314 tra i 02 27229 p2k9 27319 tr 1 27349 p349 to next routine 7 2 006 27325 adbbcb 2 004 27329 2 004 27333 wqqb 2 004 27337 ij/u 2 003 27340 293 2 001 27341 | 7 7 27349 eem 3 14 0000 0+-0 routine #294 27354 set b 0006 test aam instruction 27359 lod 8 27440 p440 in 7080 mode for wrap 27364 set b 01 0004 00 4 around. asu zones in storage. 27369 lod 8 01 27444 p4u4 27374 unl 7 01 27449 p4u9 reset memory field 27379 aam @ 27449 p449 aam 76----- to 8mnu 27384 lod 8 01 27453 p4v3 27389 cmp 4 01 27449 p4u9 cmp memory result 865u 27394 tre l 27429 p429 7 27399 tra i 01 27429 p4s9 error routine 27404 sel 2 0500 27409 wr r 27454 p454 27414 tra i 03 27424 p4b4 27419 tr 1 27429 p429 27424 hlt j 0294 27429 tra i 02 27349 p3m9 27434 tr 1 27464 p464 to next routine 7 2 006 27440 76---- 2 004 27444 8wnu 2 005 27449 2 004 27453 865u 2 003 27456 294 2 001 27457 | 7 7 27464 eem 3 14 0000 0+-0 routine #295 27469 set b 0006 test aam instruction in 27474 lod 8 27555 p555 7080 mode with a zero 27479 set b 01 0004 00 4 in storage char. 6. 27484 lod 8 01 27559 p5v9 27489 unl 7 01 27569 p5w9 +gfi in memory 27494 aam @ 27569 p569 aam 079231 to +gfi 27499 lod 8 27563 p563 27504 cmp 4 27569 p569 cmp result of +++- 27509 tre l 27544 p544 7 27514 tra i 01 27544 p5u4 error routine 27519 sel 2 0500 27524 wr r 27570 p570 27529 tra i 03 27539 p5c9 27534 tr 1 27544 p544 27539 hlt j 0295 27544 tra i 02 27464 p4o4 27549 tr 1 27579 p579 7 2 006 27555 079231 2 004 27559 +gfi 2 004 27563 +++- 2 006 27569 FI 2 003 27572 295 2 001 27573 | 7 7 7 7 routine #296 7 test of aam instruction 7 with a storage length 7 of 3. 7080 nmode 7 27579 eem 3 14 0000 0+-0 27584 set b 0006 27589 lod 8 27680 p680 lod storage with 179321 27594 set b 0003 27599 set b 01 0004 00 4 27604 lod 8 01 27684 p6y4 27609 unl 7 01 27689 p6y9 reset memory with ++++ 27614 aam @ 27689 p689 adm result equal +cba 27619 set b 0004 27624 lod 8 27694 p694 27629 cmp 4 27689 p689 27634 tre l 27669 p669 7 27639 tra i 01 27669 p6w9 error routine 27644 sel 2 0500 27649 wr r 27695 p695 27654 tra i 03 27664 p6f4 27659 tr 1 27669 p669 27664 hlt j 0296 27669 tra i 02 27579 p5p9 27674 tr 1 27704 p704 to next routine 7 2 006 27680 179321 2 004 27684 ++++ 2 005 27689 2 005 27694 +cba 2 003 27697 296 2 001 27698 | 7 7 7 routine #297 7 test of aam instruction 7 with a storage length of 7 6, in 705 iii mode. 7 27704 lem 3 15 0000 0++0 27709 set b 0006 27714 lod 8 27795 p795 lod storage with 1154c2 27719 set b 01 0004 00 4 27724 lod 8 01 27799 p7z9 27729 unl 7 01 27804 p8 4 reset memory with 08gf 27734 aam @ 27804 p804 adm result equal wt-h 27739 lod 8 27810 p810 27744 cmp 4 27804 p804 27749 tre l 27784 p784 7 27754 tra i 01 27784 p7y4 error routine 27759 sel 2 0500 27764 wr r 27811 p811 27769 tra i 03 27779 p7g9 27774 tr 1 27784 p784 27779 hlt j 0297 27784 tra i 02 27704 p7-4 27789 tr 1 27819 p819 7 2 006 27795 1154c2 2 004 27799 08gf 2 005 27804 2 006 27810 f wt-h 2 003 27813 297 2 001 27814 | 7 7 27819 lem 3 15 0000 0++0 routine #298 27824 set b 0004 test aam instruction in 27829 lod 8 27909 p909 in 705-3 mode with 27834 set b 01 0004 00 4 storage length of four. 27839 lod 8 01 27914 p9/4 27844 unl 7 01 27919 p9/9 reset memroy with c33m 27849 aam @ 27919 p919 aam storage field is 987w 27854 lod 8 27924 p924 27859 cmp 4 27919 p919 cmp aam result equal 3210 27864 tre l 27899 p899 7 27869 tra i 01 27899 p8z9 error routine 27874 sel 2 0500 27879 wr r 27925 p925 27884 tra i 03 27894 p8i4 27889 tr 1 27899 p899 27894 hlt j 0298 27899 tra i 02 27819 p8j9 27904 tr 1 27934 p934 7 2 005 27909 987w 2 005 27914 c33m 2 005 27919 2 005 27924 3210 2 003 27927 298 2 001 27928 | 7 7 routine #299 7 test of aam instruction 7 for a storage length 7 of 5, in 705 iii mode 7 27934 lem 3 15 0000 0++0 27939 set b 0005 27944 lod 8 28034 q034 lod storage with 13257 27949 set b 01 0004 00 4 27954 lod 8 01 28039 q0t9 27959 unl 7 01 28044 q0u4 reset memory with m678 27964 aam @ 28044 q044 adm result equal wt-h 27969 lod 8 01 28049 q0u9 27974 cmp 4 01 28044 q0u4 cmp aam result of g935 27979 tre l 28014 q014 7 27984 tra i 01 28014 q0/4 error routine 27989 sel 2 0500 27994 wr r 28050 q050 27999 tra i 03 28009 q0+9 28004 tr 1 28014 q014 28009 hlt j 0299 28014 tra i 02 27934 p9l4 28019 rcv u 0306 28024 tr 1 01 0204 02 4 28029 tr 1 28059 q059 to next routine 7 2 005 28034 132572 2 005 28039 m678 2 005 28044 2 005 28049 g935 2 003 28052 299 2 001 28053 | 7 7 routine #300 7 test set mac 1 to iar 7 routines using ula 7 28059 lem 3 15 0000 0++0 705 iii mode 28064 set b 0004 28069 lod 8 28154 q154 28074 unl 7 6669 reset memory field 28079 set b 0005 28084 lod 8 28159 q159 28089 ula * 6669 28094 set b 0004 28099 lod 8 28164 q164 28104 cmp 4 6669 28109 tre l 28144 q144 7 28114 tra i 01 28144 q1u4 error routine 28119 sel 2 0500 28124 wr r 28165 q165 28129 tra i 03 28139 q1c9 28134 tr 1 28144 q144 28139 hlt j 0300 28144 tra i 02 28059 q0n9 28149 tr 1 28174 q174 1 2 005 28154 99999 2 005 28159 51327 2 005 28164 0/32p 2 003 28167 300 2 001 28168 | 7 7 routine #301 7 test set mac 1 to iar 7 routines using ula 7 7080 mode 7 28174 eem 3 14 0000 0+-0 28179 set b 0004 28184 lod 8 28269 q269 28189 unl 7 159994 i99d reset memory field 28194 set b 0005 28199 lod 8 28274 q274 28204 ula * 159994 i99d set mac-1 to iar 159994 28209 set b 0004 28214 lod 8 28279 q279 28219 cmp 4 159994 i99d 28224 tre l 28259 q259 7 28229 tra i 01 28259 q2v9 error routine 28234 sel 2 0500 28239 wr r 28280 q280 28244 tra i 03 28254 q2e4 28249 tr 1 28259 q259 28254 hlt j 0301 28259 tra i 02 28174 q1p4 28264 tr 1 28289 q289 to next routine 1 2 005 28269 99999 2 005 28274 69783 2 005 28279 0r78l 2 003 28282 301 2 001 28283 | 7 7 routine #302 7 test blm 00 for execution 7 + no op che ck. use address 7 of zero. 7 28289 rcv u 28349 q349 28294 blm $ 0000 28299 trs o 10 28309 ql-9 28304 tr 1 28339 q339 7 28309 tra i 01 28339 q3t9 error routine 28314 sel 2 0500 28319 wr r 28350 q350 28324 tra i 03 28334 q3c4 28329 tr 1 28339 q339 28334 hlt j 0302 28339 tra i 02 28289 q2q9 28344 tr 1 28359 q359 1 2 005 28349 2 003 28352 302 2 001 28353 | 7 7 routine #303 7 test blm 00, with zero 7 address, for end op. 7 28359 set b 0005 28364 lod 8 28434 q434 28369 unl 7 28439 q439 28374 rcv u 28439 q439 rcv address for blm 28379 blm $ 0000 28384 cmp 4 28439 q439 check for no blanks 28389 tre l 28424 q424 7 28394 tra i 01 28424 q4s4 error routine 28399 sel 2 0500 28404 wr r 28440 q440 28409 tra i 03 28419 q4a9 28414 tr 1 28424 q424 28419 hlt j 0303 28424 tra i 02 28359 q3n9 28429 tr 1 28449 q449 to next routine 1 2 005 28434 54321 2 005 28439 2 003 28442 303 2 001 28443 | 7 7 routine #304 7 test blm 00 with address 7 0003 to check that is blanks 7 a field of 15 characters. 7 28449 set b 0005 28454 lod 8 28539 q539 28459 unl 7 28554 q554 28464 rcv u 28554 q554 28469 blm $ 0003 28474 lod 8 28569 q569 check memory for blanks 28479 cmp 4 28554 q554 28484 tre l 28519 q519 7 28489 tra i 01 28519 q5/9 error routine 28494 sel 2 0500 28499 wr r 28570 q570 28504 tra i 03 28514 q5a4 28509 tr 1 28519 q519 28514 hlt j 0304 28519 tra i 02 28449 q4m9 28524 tr 1 28579 q579 to next routine 1 2 015 28539 abcde6789303742 2 015 28554 2 015 28569 2 003 28572 304 2 001 28573 | 7 7 routine #305 7 test blm 01 for end op 7 on zero address. 7 28579 set b 0005 28584 lod 8 28654 q654 28589 unl 7 28659 q659 28594 rcv u 28655 q655 28599 blm $ 01 0000 00 0 28604 cmp 4 28659 q659 check for no blanks 28609 tre l 28644 q644 7 28614 tra i 01 28644 q6u4 error routine 28619 sel 2 0500 28624 wr r 28660 q660 28629 tra i 03 28639 q6c9 28634 tr 1 28644 q644 28639 hlt j 0305 28644 tra i 02 28579 q5p9 28649 tr 1 28669 q669 7 2 005 28654 98765 2 005 28659 2 003 28662 305 2 001 28663 | 7 7 routine #306 7 test blm 01 with address 7 0015 to check that it blanks 7 a field of 15 characters. 7 28669 set b 0005 28674 lod 8 28769 q769 28679 unl 7 28799 q799 28684 rcv u 28785 q785 28689 blm $ 01 0015 00/5 28694 lod 8 28784 q784 check for no blanks 28699 cmp 4 28799 q799 28704 tre l 28739 q739 7 28709 tra i 01 28739 q7t9 error routine 28714 sel 2 0500 28719 wr r 28800 q800 28724 tra i 03 28734 q7c4 28729 tr 1 28739 q739 28734 hlt j 0306 28739 tra i 02 28669 q6o9 28744 rcv u 0306 28749 tr 1 01 0204 02 4 28754 tr 1 28809 q809 7 2 015 28769 abcde5432198760 2 015 28784 2 015 28799 2 003 28802 306 2 001 28803 | 7 7 routine #307 7 test lo speed tmt for 7 execution + no op chk. 7 28809 set b 01 0001 00 1 28814 rcv u 28870 q870 28819 tmt 9 01 28879 q8x9 test instruction 28824 trs o 10 28834 qql4 28829 tr 1 28864 q864 7 28834 tra i 01 28864 q8w4 error routine 28839 sel 2 0500 28844 wr r 28880 q880 28849 tra i 03 28859 q8e9 28854 tr 1 28864 q864 28859 hlt j 0307 28864 tra i 02 28809 q8-9 28869 tr 1 28889 q889 to next routine 7 2 005 28874 2 005 28879 abcde 2 003 28882 307 2 001 28883 | 7 7 routine #308 7 test lo speed tmt for 7 execution + no op chk. 7 28889 set b 0005 28894 lod 8 28974 q974 28899 unl 7 28979 q979 reset rcv area 28904 set b 01 0003 00 3 28909 rcv u 28976 q976 28914 tmt 9 01 28981 q9y1 check rcv area 28919 lod 8 28984 q984 28924 cmp 4 28979 q979 28929 tr 1 28964 q964 7 28934 tra i 01 28964 q9w4 error routine 28939 sel 2 0500 28944 wr r 28985 q985 28949 tra i 03 28959 q9e9 28954 tr 1 28964 q964 28959 hlt j 0308 28964 tra i 02 28889 q8q9 28969 tr 1 28994 q994 7 2 005 28974 00000 2 005 28979 2 005 28984 0 -+0 2 003 28987 308 2 001 28988 | 7 7 routine #309 7 test lo speed tmt for 7 asu 10 for step 7 mac i +1 + step mac II +1. 7 28994 lem 3 15 0000 0++0 28999 set b 15 0005 0++5 29004 lod 8 15 0004 0++4 save original 0004 field 29009 rcv u 79999 i99r 29014 blm $ 0001 reset tmt field at 79999 29019 set b 10 0004 0--4 29024 rcv u 79999 i99r rcv at 79999 29029 tmt 9 10 79998 irrq tmt 4 blanks from 79998 29034 set b 0004 29039 lod 8 0002 29044 cmp 4 29098 r098 29049 unl 7 15 0004 0++4 put 0004 field back 29054 tr 1 29089 r089 7 29059 tra i 01 29089 r0y9 error routine 29064 sel 2 0500 29069 wr r 29099 r099 29074 tra i 03 29084 r0h4 29079 tr 1 29089 r089 29084 hlt j 0309 29089 tra i 02 28994 q9r4 29094 tr 1 29109 r109 7 2 004 29098 2 003 29101 309 2 001 29102 | 7 7 routine #310 7 test lo speed tmt 7 with asu 01 for 7 end op on storage mark. 7 29109 set b 0005 29114 lod 8 29199 r199 29119 unl 7 29204 r204 29124 set b 01 0002 00 2 reset rcv area 29129 rcv u 29203 r203 29134 tmt 9 01 29208 r2 8 tmt two characters 29139 set b 0005 29144 lod 8 29207 r207 29149 cmp 4 29214 r214 29154 tre l 29189 r189 7 29159 tra i 01 29189 r1y9 error routine 29164 sel 2 0500 29169 wr r 29215 r215 29174 tra i 03 29184 r1h4 29179 tr 1 29189 r189 29184 hlt j 0310 29189 tra i 02 29109 r1-9 29194 tr 1 29224 r224 to next routine 7 2 005 29199 00000 2 005 29204 2 005 29209 91 2 005 29214 91 2 003 29217 310 2 001 29218 | 7 7 routine #311 7 test lo speed tmt 7 with asu 12 for step 7 mac i +1 + step mac ii 7 +1 at 159999. 7 29224 eem 3 14 0000 0+-0 29229 set b 10 0005 0--5 29234 lod 8 10 0004 0--4 save original 0004 field 29239 rcv u 159999 i99i 29244 blm $ 0001 reset tmt field at 159999 29249 set b 12 0005 0+05 29254 rcv u 159999 i99i rcv at 159999 29259 tmt 9 12159996 ii9f tmt 5 blanks from 159996 29264 set b 0005 29269 lod 8 0003 29274 cmp 4 29329 r329 29279 unl 7 10 0004 0--4 put 0004 field back 29284 tre l 29319 r319 7 29289 tra i 01 29319 r3/9 error routine 29294 sel 2 0500 29299 wr r 29330 R330 29304 tra i 03 29314 r3a4 29309 tr 1 29319 r319 29314 hlt j 0311 29319 tra i 02 29224 r2k4 29324 tr 1 29339 r339 to next routine 7 2 005 29329 2 003 29332 311 2 001 29333 | 7 7 routine #312 7 test tmt 00 for transmission 7 of characters with zones only. 7 29339 set b 0005 29344 lod 8 29419 r419 29349 unl 7 29424 r424 reset rcv area 29354 rcv u 29424 r424 29359 tmt 9 29429 r429 29364 lod 8 29429 r429 check rcv area 29369 cmp 4 29424 r424 29374 tre l 29409 r409 7 29379 tra i 01 29409 r4 9 error routine 29384 sel 2 0500 29389 wr r 29430 r430 29394 tra i 03 29404 r4+4 29399 tr 1 29409 r409 29404 hlt j 0312 29409 tra i 02 29339 r3l9 29414 tr 1 29439 r439 7 2 005 29419 000000 2 005 29424 2 004 29428 +- 2 001 29429 # 2 003 29432 312 2 001 29433 | 7 7 routine #313 7 test tmt 00 for step 7 mac ii +5 at 79999. check 7 for step mac i + 5. 7 29439 lem 3 15 0000 0++0 29444 set b 14 0005 0+-5 29449 lod 8 14 0004 0+-4 save original 0004 field 29454 unl 7 14 79999 iirr reset rcv area 29459 rcv u 79999 i99r 29464 tmt 9 29534 r534 29469 set b 0010 29474 lod 8 29539 r539 29479 cmp 4 0004 29484 unl 7 14 0004 0+-4 put 0004 field back 29489 tre l 29524 r524 7 29494 tra i 01 29524 r5s4 error routine 29499 sel 2 0500 29504 wr r 29540 r540 29509 tra i 03 29519 r5a9 29514 tr 1 29524 r524 29519 hlt j 0313 29524 tra i 02 29439 r4l9 29529 tr 1 29549 r549 to next routine 7 2 009 29538 ab98cd76n 2 001 29539 # 2 003 29542 313 2 001 29543 | 7 7 routine #314 7 test tmt 00 for step 7 mac ii +5 at 159999. check 7 for step mac i + 5. 7 29549 eem 3 14 0000 0+-0 29554 set b 11 0005 0-+5 29559 lod 8 11 0004 0-+4 save original 0004 field 29564 unl 7 11159999 irii reset rcv area 29569 rcv u 159999 i99i 29574 tmt 9 29654 r654 29579 set b 0010 29584 lod 8 29659 r659 29589 cmp 4 0004 29594 unl 7 14 0004 0+-4 put 0004 field back 29599 tre l 29634 r634 7 29604 tra i 01 29634 r6t4 error routine 29609 sel 2 0500 29614 wr r 29660 r660 29619 tra i 03 29629 r6b9 29624 tr 1 29634 r634 29629 hlt j 0314 29634 tra i 02 29549 r5m9 29639 rcv u 0306 29644 tr 1 01 0204 02 4 29649 tr 1 29669 r669 7 2 009 29658 ev+0+j-gr 2 001 29659 # 2 003 29662 314 2 001 29663 | 7 7 routine #315 7 test snd for execution 7 + no op check. 7 29669 lem 3 15 0000 0++0 29674 set b 0001 29679 rcv u 29739 r739 29684 snd / 29744 r744 test instruction 29689 trs o 10 29699 ror9 29694 tr 1 29729 r729 7 29699 tra i 01 29729 r7s9 error routine 29704 sel 2 0500 29709 wr r 29745 r745 29714 tra i 03 29724 r7b4 29719 tr 1 29729 r729 29724 hlt j 0315 29729 tra i 02 29669 r6o9 29734 tr 1 29754 r754 to next routine 7 2 005 29739 2 005 29744 +- 96 2 003 29747 315 2 001 29748 | 7 7 routine #316 7 test snd for step mac i 7 + mac II +5 7 29754 eem 3 14 0000 0+-0 29759 set b 0015 29764 lod 8 29874 r874 29769 unl 7 29889 r889 reset rcv area 29774 set b 0003 29779 rcv u 29879 r879 29784 snd / 29849 r849 29789 set b 0015 29794 lod 8 29859 r859 check rcv area 29799 cmp 4 29889 r889 29804 tre l 29839 r839 7 29809 tra i 01 29839 r8t9 error routine 29814 sel 2 0500 29819 wr r 29890 r890 29824 tra i 03 29834 r8c4 29829 tr 1 29839 r839 29834 hlt j 0316 29839 tra i 02 29754 r7n4 29844 tr 1 29899 r899 7 2 015 29859 9650+ -1638ij/o 2 015 29874 000000000000000 2 015 29889 2 003 29892 316 2 001 29893 | 7 7 routine #317 7 test snd for end op 7 on sm with a storage 7 length of zero. 7 29899 eem 3 14 0000 0+-0 29904 set b 0005 29909 lod 8 29994 r994 29914 unl 7 29999 r999 set rcv area 29919 set b 0000 29924 rcv u 29999 r999 29929 snd / 30004 +004 29934 set b 0005 29939 lod 8 29999 r999 check rcv area 29944 cmp 4 29994 r994 29949 tre l 29984 r984 7 29954 tra i 01 29984 r9y4 error routine 29959 sel 2 0500 29964 wr r 30005 +005 29969 tra i 03 29979 r9g9 29974 tr 1 29984 r984 29979 hlt j 0317 29984 tra i 02 29899 r8r9 29989 tr 1 30014 +014 to next routine 7 2 005 29994 uuuuu 2 005 29999 2 005 30004 33333 2 003 30007 317 2 001 30008 | 7 7 routine #318 7 test snd for step 7 mac i +5 at 79999. 7 30014 lem 3 15 0000 0++0 30019 set b 08 0005 0-05 30024 lod 8 08 0004 0-04 save original 0004 field 30029 unl 7 08 30144 +j44 reset rcv area 30034 set b 0010 30039 lod 8 30134 +134 30044 unl 7 0004 put snd field at 0004 30049 set b 0002 30054 rcv u 30139 +139 30059 snd / 79999 i99r 30064 set b 0010 30069 lod 8 30134 +134 30074 cmp 4 30144 +144 30079 unl 7 08 0004 0-04 put original field back 30084 tre l 30119 +119 7 30089 tra i 01 30119 +1/9 error routine 30094 sel 2 0500 30099 wr r 30145 +145 30104 tra i 03 30114 +1a4 30109 tr 1 30119 +119 30114 hlt j 0318 30119 tra i 02 30014 +0j4 30124 tr 1 30154 +154 to next routine 7 2 010 30134 +- +-Arw4 2 010 30144 2 003 30147 318 2 001 30148 | 7 7 routine #319 7 test snd for step 7 mac i +5 at 159999. 7 30154 eem 3 14 0000 0+-0 30159 set b 09 0005 0- 5 30164 lod 8 09 0004 0- 4 save original 0004 field 30169 unl 7 09 30284 +ky4 reset rcv area 30174 set b 0010 30179 lod 8 30274 +274 30184 unl 7 0004 put snd field at 0004 30189 set b 0002 30194 rcv u 30279 +279 30199 snd / 159999 i99i 30204 set b 0010 30209 lod 8 30274 +274 30214 cmp 4 30284 +284 30219 unl 7 09 0004 0- 4 put original field back 30224 tre l 30259 +259 7 30229 tra i 01 30259 +2v9 error routine 30234 sel 2 0500 30239 wr r 30285 +285 30244 tra i 03 30254 +2e4 30249 tr 1 30259 +259 30254 hlt j 0319 30259 tra i 02 30154 +1n4 30264 tr 1 30294 +294 to next routine 7 2 010 30274 5rwa-+ -+ 2 010 30284 2 003 30287 319 2 001 30288 | 7 7 routine #320 7 test snd chk memory for 7 execution + no op chk. 7 30294 rww s 19994 z994 30299 snd / 19994 z994 30304 trs o 10 30314 +lj4 30309 tr 1 30344 +344 7 30314 tra i 01 30344 +3u4 error routine 30319 sel 2 0500 30324 wr r 30350 +350 30329 tra i 03 30339 +3c9 30334 tr 1 30344 +344 30339 hlt j 0320 30344 tra i 02 30294 +2r4 30349 tr 1 30359 +359 7 2 003 30352 320 2 001 30353 | 7 7 routine #321 7 test snd chk memory 7 to check that no transmission 7 of data takes place. 7 30359 set b 0010 30364 lod 8 30459 +459 30369 unl 7 30469 +469 reset rcv areA 30374 lod 8 30479 +479 30379 unl 7 19999 z999 set up a field at 19999 30384 set b 01 0002 00 2 30389 rww s 30464 +464 30394 snd / 19994 z994 30399 lod 8 30469 +469 30404 cmp 4 30459 +459 check rcv area 30409 tre l 30444 +444 7 30414 tra i 01 30444 +4u4 error routine 30419 sel 2 0500 30424 wr r 30480 +480 30429 tra i 03 30439 +4c9 30434 tr 1 30444 +444 30439 hlt j 0321 30444 tra i 02 30359 +3n9 30449 tr 1 30489 +489 7 2 010 30459 0000000000 2 010 30469 2 010 30479 1234567890 2 003 30482 321 2 001 30483 | 7 7 routine #322 7 test snd chk memory 7 to check for tf on rww 7 tgr on snd. 7 30489 rww s 19994 z994 30494 snd / 19994 z994 should tf rww trigger 30499 set b 0005 30504 lod 8 30599 +599 30509 unl 7 30604 +604 reset rcv areA 30514 set b 0001 30519 rcv u 30604 +604 set up a field at 19999 30524 snd / 30609 +609 30529 set b 0005 30534 lod 8 30609 +609 30539 cmp 4 30604 +604 check rcv area 30544 tre l 30579 +579 7 30549 tra i 01 30579 +5x9 error routine 30554 sel 2 0500 30559 wr r 30610 +610 30564 tra i 03 30574 +5g4 30569 tr 1 30579 +579 30574 hlt j 0322 30579 tra i 02 30489 +4q9 30584 rcv u 0306 30589 tr 1 01 0204 02 4 30594 tr 1 30619 +619 7 2 005 30599 00000 2 005 30604 2 005 30609 +- 96 2 003 30612 322 2 001 30613 | 7 30619 eem 3 14 0000 0+-0 routine #323 30624 set b 0000 execute tct and test 900 30629 set b 0010 and 901. field is 111112222 30634 unl 7 30729 +729 30639 rcv u 30729 +729 30644 tct , 08 30719 +P19 30649 trs o 10 30674 +op4 30654 trs o 11 30674 +og4 30659 lod 8 30719 +719 30664 cmp 4 30729 +729 30669 tre l 30704 +704 7 30674 tra i 01 30704 +7 4 error routine 30679 sel 2 0500 30684 wr r 30730 +730 30689 tra i 03 30699 +6I9 30694 tr 1 30704 +704 30699 hlt j 0323 30704 tra i 02 30619 +6j9 30709 tr 1 30739 +739 7 2 009 30718 111112222 2 001 30719 # 2 010 30729 0000000000 rcv field 2 003 30732 323 2 001 30733 | 7 30739 eem 3 14 0000 0+-0 routine #324 30744 rcv u 30829 +829 test tct with indirect 30749 eia , 10 0000 0--0 address. test mac-2 step 30754 tct , 08 30764 +p64 plus 10 on tct. 30759 nop a 0000 30764 nop a 30829 +829 30769 trs o 10 30784 +pq4 test 900 30774 tzb . 03 30784 +7h4 30779 tzb . 05 30814 +y/4 test macII test plus 10 7 30784 tra i 01 30814 +8/4 error routine 30789 sel 2 0500 30794 wr r 30830 +830 30799 tra i 03 30809 +8+9 30804 tr 1 30814 +814 30809 hlt j 0324 30814 tra i 02 30739 +7l9 30819 tr 1 30844 +844 to next routine 7 2 009 30828 111112222 2 001 30829 # 2 003 30832 324 2 001 30833 | 2 006 30839 444444 7 30844 eem 3 14 0000 0+-0 routine #325 30849 set b 0000 test tct using a 30 30854 set b 0030 character field. 30859 unl 7 30989 +989 30864 sb % 13 30969 +iw9 make a record mk in rcv area 30869 rcv u 30969 +969 30874 tct , 08 30939 +r39 30879 lod 8 30959 +959 30884 cmp 4 30989 +989 30889 tre l 30924 +924 7 30894 tra i 01 30924 +9s4 error routine 30899 sel 2 0500 30904 wr r 30990 +990 30909 tra i 03 30919 +9a9 30914 tr 1 30924 +924 30919 hlt j 0325 30924 tra i 02 30844 +8m4 30929 tr 1 30999 +999 to next routine 7 2 004 30933 aaaa 2 001 30934 # 2 024 30958 -----gggggzzzzz#####NNNN tct field 2 001 30959 # 2 030 30989 rcv field 2 003 30992 324 2 001 30993 | 7 7 routine #326 7 test step mac 1 minus one at 7 memory boundry according 7 to 705-3 or 7080 mode. 7 30999 eem 3 14 0000 0+-0 7080 mode 31004 set b 01 0005 00 5 31009 lod 8 01 0004 00 4 save char. at 00004 31014 set b 02 0005 00-5 31019 lod 8 02 31154 a1n4 12345 into asu 02 31024 set b 03 0005 00+5 31029 lod 8 03 31159 a1e9 abcde into asu 03 31034 unl 7 03 0004 00+4 adcde to 00004 31039 set b 0010 7 31044 unl 7 02159999 i9ri 12345 to 159999 31049 cmp 4 02 79999 i9rr cmp vs 79999 31054 tre l 31079 a079 if equal-no 80k 7 31059 lod 8 31159 a159 lod 12345abcde 31064 cmp 4 0004 step mac-1 00000 to 159999 31069 tre l 31079 a079 31074 tr 1 31109 a109 7 31079 lem 3 15 0000 0++0 705-3 mode 31084 unl 7 03 79999 i9ir abcde to 79999 31089 lod 8 31164 a164 lod abcdeabcde 31094 cmp 4 0004 step mac-1 00000 to 79999 31099 unl 7 01 0004 00 4 restore field at 0004. 31104 tre l 31144 a144 7 31109 unl 7 01 0004 00 4 31114 tra i 01 31144 a1u4 error routine 31119 sel 2 0500 31124 wr r 31165 a165 31129 tra i 03 31139 a1c9 31134 tr 1 31144 A144 31139 hlt j 0326 31144 tra i 02 30999 +9r9 31149 tr 1 31174 a174 to next routine 7 2 005 31154 12345 2 005 31159 abcde 2 005 31164 abcde 2 003 31167 326 2 001 31168 | 7 7 7 routine #327 7 test step ic 80k on 7 in 7080 mode. 7 31174 eem 3 14 0000 0+-0 31179 set b 0005 31184 lod 8 31204 a204 31189 unl 7 79999 i99r put tr 01 in 79999 31194 rcv u 31266 a266 31199 tr 1 79999 i99r transfer to 79999 31204 tr 1 01 31209 a2 9 7 31209 lod 8 31264 a264 31214 cmp 4 31269 a269 31219 tre l 31254 a254 7 31224 tra i 01 31254 a2v4 error routine 31229 sel 2 0500 31234 wr r 31270 a270 31239 tra i 03 31249 a2d9 31244 tr 1 31254 a254 31249 hlt j 0327 31254 tra i 02 31174 a1p4 31259 tr 1 31279 a279 7 2 005 31264 0000U 2 005 31269 0 rcv area 2 003 31272 327 2 001 31273 | 7 7 7 routine #328 7 test wrap around of ic 7 from 79999 to 00004 in 7 705-3 mode. 7 31279 lem 3 15 0000 0++0 31284 set b 0005 31289 lod 8 31309 a309 31294 unl 7 79999 i99r put tr 01 in 79999 31299 rcv u 31371 a371 31304 tr 1 79999 i99r transfer to 79999 31309 tr 1 01 31314 a3/4 7 31314 lod 8 31369 a369 31319 cmp 4 31374 a374 31324 tre l 31359 a359 7 31329 tra i 01 31359 a3v9 error routine 31334 sel 2 0500 31339 wr r 31375 a375 31344 tra i 03 31354 a3e4 31349 tr 1 31359 a359 31354 hlt j 0328 31359 tra i 02 31279 a2p9 31364 tr 1 31384 a384 to next routine 7 2 005 31369 00004 2 005 31374 0 rcv area 2 003 31377 328 2 001 31378 | 7 7 7 routine #329 7 test wrap around of ic 7 from 159999 to 00004 in 7 in 7080 mode. 7 31384 eem 3 14 0000 0+-0 31389 set b 0005 31394 lod 8 31414 a414 31399 unl 7 159999 i99i put tr 01 in 159999 31404 rcv u 31486 a486 31409 tr 1 159999 i99i transfer to 159999 31414 tr 1 01 31419 a4/9 7 31419 lod 8 31484 a484 31424 cmp 4 31489 a489 31429 tre l 31464 a464 7 31434 tra i 01 31464 a4w4 error routine 31439 sel 2 0500 31444 wr r 31490 a490 31449 tra i 03 31459 a4e9 31454 tr 1 31464 a464 31459 hlt j 0329 31464 tra i 02 31384 a3q4 31469 rcv u 0306 31474 tr 1 01 0204 02 4 31479 tr 1 31564 a564 to next routine 7 2 005 31484 00004 2 005 31489 0 rcv area 2 003 31492 329 2 001 31493 | 7 7 routine #340 7 execute chr, eim, lim 7 and test 900, 901. 7 31564 nop a 37294 g294 sw-bypass if chan. operation 7 31569 eem 3 14 0000 0+-0 31574 chr 3 13 0000 0+ 0 execute chr 31579 eim , 06 0000 0 -0 eim and 31584 lim , 07 0000 0 +0 lim 31589 trs o 10 31604 ao-4 test 900 31594 trs o 11 31604 ao+4 test 901 31599 tr 1 31634 a634 7 31604 tra i 01 31634 a6t4 error routine 31609 sel 2 0500 31614 wr r 31650 a650 31619 tra i 03 31629 a6b9 31624 tr 1 31634 a634 31629 hlt j 0340 31634 tra i 02 31564 a5o4 31639 rcv u 0306 31644 tr 1 01 0204 02 4 31649 tr 1 31659 a659 to next routine 7 2 003 31652 340 2 001 31653 | 7 7 routine #341 7 execute lip 0009, test all 7 check triggers for off 7 after lip. error switch 7 is in case ic sets wrong to wr 7 31659 eem 3 14 0000 0+-0 31664 nop a 31759 a759 switch- tr if error in set ic 31669 spc , 3700 on last pass. 31674 set b 0008 31679 lod 8 31812 a812 lod ic and status -+-- in casu 31684 set b 0032 15, zerso in rest of casu 15 31689 spc , 0000 7 31694 sgn t 31660 a660 set sw to tr 31699 lip , 15 0009 0++9 on lip-go to test 900 chk 31704 tr 1 31759 a759 error 7 31709 trs o 10 31759 apn9 error 31714 trs o 11 31759 ape9 error 31719 trs o 12 31759 ag59 error 31724 trs o 13 31759 agv9 error 31729 trs o 14 31759 agn9 error 31734 trs o 15 31759 age9 error 31739 tra i 31759 a759 error 7 31744 sb % 13 31660 afw0 reset switch 31749 sb % 14 31660 afo0 on good 31754 tr 1 31799 a799 31759 sb % 13 31660 afw0 reset switch 31764 sb % 14 31660 afo0 on error 7 31769 tra i 01 31799 a7z9 error routine 31774 sel 2 0500 31779 wr r 31813 a813 31784 tra i 03 31794 a7i4 31789 tr 1 31799 a799 31794 hlt j 0341 31799 tra i 02 31659 a6n9 31804 tr 1 31824 a824 to next routine 7 2 004 31808 -+-- status for lip 3 31812 31709 a709 ic for lip 2 003 31815 341 2 001 31816 | 7 7 routine #342 7 do lip 0009 to test set 7 ic 9999 from wr. 7 error switch is in case 7 ic does not set correctly. 7 31824 eem 3 14 0000 0+-0 31829 nop a 31909 a909 switch- tr if error in set ic 31834 spc , 3700 on last pass. 31839 set b 0005 31844 lod 8 31884 a884 lod return tranfer 31849 unl 7 9999 unl to 9999 31854 set b 0008 31859 lod 8 31962 a962 lod ic and status -+-- in casu 31864 set b 0032 15, zerso in rest of casu 15 31869 spc , 0000 7 31874 sgn t 31825 a825 set error switch 31879 lip , 15 0009 0++9 lip to 9999 31884 tr 1 31889 a889 7 31889 spc , 0000 31894 sb % 13 31825 ahs5 reset error 31899 sb % 14 31825 ahk5 switch on good 31904 tr 1 31949 a949 7 31909 sb % 13 31825 ahs5 reset error 31914 sb % 14 31825 ahk5 switch on error 7 31919 tra i 01 31949 a9u9 error routine 31924 sel 2 0500 31929 wr r 31963 a963 31934 tra i 03 31944 a9d4 31939 tr 1 31949 a949 31944 hlt j 0342 31949 tra i 02 31824 a8k4 31954 tr 1 31974 a974 to next routine 7 2 008 31962 -+--9999 status and ic for lip 2 003 31965 342 2 001 31966 | 7 7 routine #343 7 do lip 0009 to test set 7 ic 6664 from wr. 7 error switch is in case 7 ic does not set correctly. 7 31974 eem 3 14 0000 0+-0 31979 nop a 32059 b059 switch- tr if error in set ic 31984 spc , 3700 on last pass. 31989 set b 0005 31994 lod 8 32034 b034 lod return tranfer 31999 unl 7 6664 unl to 6664 32004 set b 0008 32009 lod 8 32112 b112 lod ic and status in casu 15 32014 set b 0032 rest of casu 15 is zero 32019 spc , 0000 7 32024 sgn t 31975 a975 set error switch 32029 lip , 15 0009 0++9 lip to 9999 32034 tr 1 32039 b039 7 32039 spc , 0000 32044 sb % 13 31975 Aix5 reset error 32049 sb % 14 31975 aip5 switch on good 32054 tr 1 32099 b099 7 32059 sb % 13 31975 aix5 reset error 32064 sb % 14 31975 aip5 switch on error 7 32069 tra i 01 32099 b0z9 error routine 32074 sel 2 0500 32079 wr r 32113 b113 32084 tra i 03 32094 b0i4 32089 tr 1 32099 b099 32094 hlt j 0343 32099 tra i 02 31974 a9p4 32104 tr 1 32124 b124 to next routine 7 2 008 32112 -+--6664 status and ic for lip 2 003 32115 343 2 001 32116 | 7 7 routine #344 7 do lip 0009 to test set 7 ic 159004 from wr. 7 error switch is in case 7 ic does not set correctly. 7 32124 eem 3 14 0000 0+-0 32129 spc , 0000 32134 set b 01 0005 00 5 32139 lod 8 01159004 i0 d save data at 159004 7 32144 nop a 32229 b229 switch- tr if error in set ic 32149 spc , 3700 on last pass. 32154 set b 0005 32159 lod 8 32199 b199 lod return tranfer 32164 unl 7 159004 i00d unl to 159004 32169 set b 0008 32174 lod 8 32287 b287 lod ic and status in casu 15 32179 set b 0032 rest of casu 15 is zero 32184 spc , 0000 7 32189 sgn t 32140 b140 set error switch 32194 lip , 15 0009 0++9 lip to 159004 32199 tr 1 32204 b204 7 32204 spc , 0000 32209 unl 7 01159004 i0 d replace data at 159004 32214 sb % 13 32140 bau0 reset error 32219 sb % 14 32140 bam0 switch on good 32224 tr 1 32274 b274 7 32229 unl 7 01159004 i0 d replace data at 159004 32234 sb % 13 32140 bau0 reset error 32239 sb % 14 32140 bam0 switch on error 7 32244 tra i 01 32274 b2x4 error routine 32249 sel 2 0500 32254 wr r 32288 b288 32259 tra i 03 32269 b2f9 32264 tr 1 32274 b274 32269 hlt j 0344 32274 tra i 02 32124 b1k4 32279 tr 1 32299 b299 to next routine 7 2 008 32287 -+--i00d 2 003 32290 344 2 001 32291 | 7 7 routine #345 7 do lip 0009 to test set 7 status for wr. 7 status is k--d. 7 32299 eem 3 14 0000 0+-0 32304 spc , 3700 32309 set b 0008 lod ic and status in casu 15 32314 lod 8 32462 b462 rest of casu is zero 32319 set b 0032 7 32324 spc , 0000 32329 rad h 32470 b470 acc minus on, acc dzt off 32334 rad h 01 32470 b4x0 asu minus on, asu dzt off 32339 cmp 4 01 32470 b4x0 hi on, lo off 32344 lip , 15 0009 0++9 7 32349 trh k 32419 b419 test that hi is off 32354 tre l 32419 b419 and lo is on 32359 trp m 32369 b369 test acc plus 32364 tr 1 32419 b419 error 32369 trp m 01 32379 b3x9 test acc plus 32374 tr 1 32419 b419 error 32379 trz n 32389 b389 test acc zero 32384 tr 1 32419 b419 error 32389 trz n 01 32399 b3z9 test acc zero 32394 tr 1 32419 b419 error 32399 lda = 32404 b404 test 7080 mode off 32404 nop a 000z using lda 32409 cmp 4 32468 b468 32414 tre l 32449 b449 7 32419 tra i 01 32449 b4u9 error routine 32424 sel 2 0500 32429 wr r 32471 b471 32434 tra i 03 32444 b4d4 32439 tr 1 32449 b449 32444 hlt j 0345 32449 tra i 02 32299 b2r9 32454 tr 1 32479 b479 to next routine 7 2 004 32458 k--d status bits 3 32462 32349 b349 ic 2 008 32470 x00009-j 2 003 32473 345 2 001 32474 | 7 7 routine #346 7 do lip 0009 to test set 7 status for wr. 7 status is j+-l. 7 32479 eem 3 14 0000 0+-0 32484 spc , 3700 32489 set b 0008 lod ic and status in casu 15 32494 lod 8 32627 b627 rest of casu is zero 32499 set b 0032 7 32504 spc , 0000 32509 rad h 32629 b629 acc plus and zero 32514 rad h 01 32629 b6s9 asu plus and zero 32519 cmp 4 01 32630 b6t0 hi off and lo on. 32524 lip , 15 0009 0++9 lip to reverse status, 7080 32529 nop a 0000 mode is not reversed. 7 32534 tre l 32584 b584 test that 32539 trh k 32549 b549 hi is on and lo is off 32544 tr 1 32584 b584 32549 trp m 32584 b584 test acc plus 32554 trp m 01 32584 b5y4 test asu minus 32559 trz n 32584 b584 test acc dzt off 32564 trz n 01 32584 b5y4 test asu dzt off 32569 cno , 11 0000 0-+0 32574 trs o 10 32584 bnq4 32579 tr 1 32614 b614 7 32584 tra i 01 32449 b4u9 error routine 32589 sel 2 0500 32594 wr r 32471 b471 32599 tra i 03 32444 b4d4 32604 tr 1 32449 b449 32609 hlt j 0346 32614 tra i 02 32299 b2r9 32619 tr 1 32639 b639 to next routine 7 2 004 32623 j+-l status for lip 3 32627 32529 b529 ic for lip 2 003 32630 *+9 2 003 32633 346 2 001 32634 | 7 7 routine #347 7 do lip 0009 for no 7 storing of ic and status. 7 32639 eem 3 14 0000 0+-0 32644 spc , 3700 32649 set b 0008 lod ic and status in casu 15 32654 lod 8 32742 b742 rest of casu is zero 32659 set b 0032 7 32664 spc , 0000 32669 set b 0000 clear word 000 32674 set b 0008 in bank 0 to zeros. 32679 lip , 15 0009 0++9 do lip 32684 spc , 0000 32689 set b 0008 test bank 0 word 000 32694 trz n 32729 b729 for zero 7 32699 tra i 01 32729 b7s9 error routine 32704 sel 2 0500 32709 wr r 32743 b743 32714 tra i 03 32724 b7b4 32719 tr 1 32729 b729 32724 hlt j 0347 32729 tra i 02 32639 b6l9 32734 tr 1 32754 b754 to next routine 7 2 004 32738 -+-- status for lip 3 32742 32684 b684 ic for lip 2 003 32745 347 2 001 32746 | 7 7 routine #348 7 test store ic and status. 7 use lip 0000 to test store 7 ic value 9999. 7 32754 eem 3 14 0000 0+-0 32759 spc , 0000 32764 set b 0010 32769 lod 8 32809 b809 put lip 0000 and transfer 32774 unl 7 9999 instructions at 9999 32779 spc , 3700 32784 set b 0008 32789 lod 8 32877 b877 lod ic and status in casu 15 32794 set b 0032 rest of casu 15 is zero 32799 tr 1 9994 7 32804 lip , 15 0000 0++0 these two instructions 32809 tr 1 32834 b834 are placed at 9999 7 32814 spc , 0000 after lip, 32819 set b 0004 compare ic value stored 32824 cmp 4 32881 b881 versus correct value 9999. 32829 tre l 32864 b864 7 32834 tra i 01 32864 b8w4 error routine 32839 sel 2 0500 32844 wr r 32882 b882 32849 tra i 03 32859 b8e9 32854 tr 1 32864 b864 32859 hlt j 0348 32864 tra i 02 32754 b7n4 32869 tr 1 32894 b894 to next routine 7 2 004 32873 j+-- status for lip 3 32877 32814 b814 ic for lip 2 004 32881 9999 correct ic value stored 2 003 32884 348 2 001 32885 | 7 7 routine #349 7 test store ic and status. 7 use lip 0000 to test store 7 ic value 6664. 7 32894 eem 3 14 0000 0+-0 32899 spc , 0000 32904 set b 0010 32909 lod 8 32949 b949 put lip 0000 and transfer 32914 unl 7 6664 instructions at 6664 32919 spc , 3700 32924 set b 0008 32929 lod 8 33017 c017 lod casu 15 with ic and status 32934 set b 0032 rest of casu 15 is zero 32939 tr 1 6659 7 32944 lip , 15 0000 0++0 these two instructions 32949 tr 1 32954 b954 are placed at 6664 7 32954 spc , 0000 after lip, 32959 set b 0004 compare ic value stored 32964 cmp 4 33021 c021 versus correct value 6664. 32969 tre l 33004 c004 7 32974 tra i 01 33004 c0 4 error routine 32979 sel 2 0500 32984 wr r 33022 c022 32989 tra i 03 32999 b9i9 32994 tr 1 33004 c004 32999 hlt j 0349 33004 tra i 02 32894 b8r4 33009 tr 1 33034 c034 to next routine 7 2 004 33013 -+-- status for lip 3 33017 32954 b954 ic for lip 2 004 33021 6664 correct ic value stored 2 003 33024 349 2 001 33025 | 7 7 routine #350 7 test store ic and status. 7 use lip 0000 to test store 7 ic value 150009. 7 33034 eem 3 14 0000 0+-0 33039 spc , 0000 33044 set b 01 0010 00/0 33049 lod 8 01150009 +0 i save data at 150009 33054 set b 0010 33059 lod 8 33099 c099 put lip 0000 and transfer 33064 unl 7 150009 +00i instructions at 150009 33069 spc , 3700 33074 set b 0008 33079 lod 8 33182 c182 lod casu 15 with ic and status 33084 set b 0032 rest of casu 15 is zero 33089 tr 1 150004 +00d 7 33094 lip , 15 0000 0++0 these two instructions 33099 tr 1 33104 c104 are placed at 150009 7 33104 spc , 0000 after lip, 33109 unl 7 01150009 +0 i replace data at 150009 33114 set b 0004 compare ic value stored 33119 cmp 4 33186 c186 versus correct value +00i 33124 tre l 33159 c159 7 33129 tra i 01 33159 c1v9 error routine 33134 sel 2 0500 33139 wr r 33187 c187 33144 tra i 03 33154 c1e4 33149 tr 1 33159 c159 33154 hlt j 0350 33159 tra i 02 33034 c0l4 33164 rcv u 0306 33169 tr 1 01 0204 02 4 33174 tr 1 33199 c199 to next routine 7 2 004 33178 -+-- status for lip 3 33182 33104 c104 ic for lip 2 004 33186 +00i correct ic value stored 2 003 33189 350 2 001 33190 | 7 7 routine #351 7 test store ic and status. 7 use lip 3700 to test store 7 a status of -+--. 7 33199 eem 3 14 0000 0+-0 33204 spc , 3700 33209 set b 0000 33214 set b 0032 clear casu 15 to zeros 33219 spc , 0000 33224 rad h 33317 c317 acc plus and dzt off 33229 rad h 01 33317 c3/7 asu plus and dzt off 33234 cmp 4 01 33315 c3/5 hi and lo off 33239 lip , 15 3700 3g+0 do lip to store status 33244 spc , 3704 33249 set b 0004 33254 cmp 4 33321 c321 cmp status stored 33259 spc , 0000 33264 tre l 33299 c299 7 33269 tra i 01 33299 c2z9 error routine 33274 sel 2 0500 33279 wr r 33322 c322 33284 tra i 03 33294 c2i4 33289 tr 1 33299 c299 33294 hlt j 0351 33299 tra i 02 33199 c1r9 33304 rcv u 0306 33309 tr 1 01 0204 02 4 33314 tr 1 33334 c334 to next routine 7 2 003 33317 1 a 2 004 33321 -+-- correct status stored 2 003 33324 351 2 001 33325 | 7 7 routine #352 7 test store ic and status. 7 use lip 3700 to test store 7 status with no bit pickup from 7 sbr thru alu to stor sw. 7 33334 eem 3 14 0000 0+-0 33339 spc , 3700 33344 set b 0000 33349 set b 0032 clear casu 15 to zeros 33354 spc , 0004 33359 rad h 33468 c468 acc plus and dzt off 33364 rad h 01 33468 c4w8 asu plus and dzt off 33369 cmp 4 01 33466 c4w6 hi and lo off 33374 lfc , 02 33479 c4p9 group marks into char. 4,5,6,7 33379 spc , 0000 33384 lfc , 02 33484 c4q4 group marks into sbr 4-7. 7 33389 lip , 15 3700 3g+0 do lip to store status 33394 spc , 3704 33399 set b 0004 33404 cmp 4 33472 c472 cmp status stored 33409 spc , 0000 33414 tre l 33449 c449 7 33419 tra i 01 33449 c4u9 error routine 33424 sel 2 0500 33429 wr r 33473 c473 33434 tra i 03 33444 c4d4 33439 tr 1 33449 c449 33444 hlt j 0352 33449 tra i 02 33334 c3l4 33454 rcv u 0306 33459 tr 1 01 0204 02 4 33464 tr 1 33489 c489 to next routine 7 2 004 33468 1 a 2 004 33472 -+-- correct status stored 2 003 33475 352 2 001 33476 | 2 001 33477 | 2 001 33478 | 2 001 33479 | 2 005 33484 000000 7 7 routine #353 7 test store ic and status. 7 use lip 3700 to test store 7 a status of j+-l 7 33489 eem 3 14 0000 0+-0 33494 spc , 3700 33499 set b 0000 33504 set b 0032 clear casu 15 to zeros 33509 spc , 0004 33514 rad h 33611 c611 acc minus and dzt off 33519 rad h 01 33611 c6/1 asu minus and dzt off 33524 cmp 4 01 33611 c6/1 hi on, lo off 7 33529 lip , 15 3700 3g+0 do lip to store status 33534 trs o 11 33564 cnf4 test 901 33539 spc , 3704 33544 set b 0004 33549 cmp 4 33615 c615 cmp status stored 33554 spc , 0000 33559 tre l 33594 c594 7 33564 tra i 01 33594 c5z4 error routine 33569 sel 2 0500 33574 wr r 33616 c616 33579 tra i 03 33589 c5h9 33584 tr 1 33594 c594 33589 hlt j 0353 33594 tra i 02 33489 c4q9 33599 rcv u 0306 33604 tr 1 01 0204 02 4 33609 tr 1 33624 c624 to next routine 7 2 002 33611 xj 2 004 33615 j+-l correct status stored 2 003 33618 353 2 001 33619 | 7 7 routine #354 7 test store ic and status. 7 use lip 3700 to test store 7 a status of k+-d 7 33624 eem 3 14 0000 0+-0 33629 spc , 3700 33634 set b 0000 33639 set b 0032 clear casu 15 to zeros 33644 spc , 0004 33649 rad h 33747 c747 acc plux and dzt on 33654 rad h 01 33747 c7u7 asu plus and dzt on 33659 cmp 4 01 33745 c7u5 hi off, lo on 7 33664 lip , 15 3700 3g+0 do lip to store status 33669 trs o 11 33699 coi9 test 901 33674 spc , 3704 33679 set b 0004 33684 cmp 4 33751 c751 cmp status stored 33689 spc , 0000 33694 tre l 33729 c729 7 33699 tra i 01 33729 c7s9 error routine 33704 sel 2 0500 33709 wr r 33752 c752 33714 tra i 03 33724 c7b4 33719 tr 1 33729 c729 33724 hlt j 0354 33729 tra i 02 33624 c6k4 33734 rcv u 0306 33739 tr 1 01 0204 02 4 33744 tr 1 33764 c764 to next routine 7 2 003 33747 1 + 2 004 33751 k+-d correct status stored 2 003 33754 354 2 001 33755 | 7 7 routine #355 7 test store ic and status. 7 use lip 3700 to test store 7 status four times. 7 test 901 each time 7 33764 eem 3 14 0000 0+-0 33769 spc , 3700 33774 set b 0008 33779 lod 8 33952 c952 lod ic and status -+-0 33784 set b 0032 33789 lip , 15 0009 0++9 lip to set status 33794 lip , 15 3700 3g+0 lip to store status 33799 trs o 11 33899 cqi9 test 901 and dzt on 7 33804 spc , 3700 33809 set b 0008 33814 lod 8 33960 c960 lod ic and status -+-a 33819 lip , 15 0009 0++9 lip to set status 33824 lip , 15 3700 3g+0 lip to store status 33829 trs o 11 33899 cqi9 test 901 and dzt on 7 33834 spc , 3700 33839 set b 0008 33844 lod 8 33968 c968 lod ic and status -+-a 33849 lip , 15 0009 0++9 lip to set status 33854 lip , 15 3700 3g+0 lip to store status 33859 trs o 11 33899 cqi9 test 901 and dzt on 7 33864 spc , 3700 33869 set b 0008 33874 lod 8 33976 c976 lod ic and status -+-a 33879 lip , 15 0009 0++9 lip to set status 33884 lip , 15 3700 3g+0 lip to store status 33889 trs o 11 33899 cqi9 test 901 and dzt on 33894 tr 1 33929 c929 7 33899 tra i 01 33929 c9s9 error routine 33904 sel 2 0500 33909 wr r 33977 c977 33914 tra i 03 33924 c9b4 33919 tr 1 33929 c929 33924 hlt j 0355 33929 tra i 02 33764 c7o4 33934 rcv u 0306 33939 tr 1 01 0204 02 4 33944 tr 1 33989 c989 to next routine 7 2 004 33948 -+-0 status for first lip 3 33952 33794 c794 ic value 2 004 33956 -+-a status for first lip 3 33960 33824 c824 ic value 2 004 33964 -+-j status for first lip 3 33968 33854 c854 ic value 2 004 33972 l+-+ status for first lip 3 33976 33884 c884 ic value 2 003 33979 355 2 001 33980 | 7 7 routine #356 7 execute tip and test 900. 7 test store ic and status 7 during tip. 7 33989 eem 3 14 0000 0+-0 33994 spc , 3700 33999 set b 0000 34004 set b 0032 clear casu 15 to zeros 34009 spc , 0000 34014 rad h 34122 d122 turn off 34019 rad h 01 34122 d1s2 status 34024 cmp 4 01 34120 d1s0 triggers 7 34029 tip , 14 34039 d+l9 do tip 34034 tr 1 34064 d064 error 34039 trs o 10 34064 d-o4 test 900 34044 spc , 3700 34049 set b 0008 34054 cmp 4 34130 d130 cmp ic and status stored 34059 tre l 34074 d074 during tip. 7 34064 lip , 15 3700 3g+0 tf int prog. 34069 tr 1 34084 d084 on error 34074 lip , 15 3700 3g+0 tf int prog. 34079 tr 1 34114 d114 on good 7 34084 tra i 01 34114 d1/4 error routine 34089 sel 2 0500 34094 wr r 34131 d131 34099 tra i 03 34109 d1+9 34104 tr 1 34114 d114 34109 hlt j 0356 34114 tra i 02 33989 c9q9 34119 tr 1 34139 d139 to next routine 7 2 003 34122 1 a 2 004 34126 -+-- correct status stored 3 34130 34034 d034 correct ic value 2 003 34133 356 2 001 34134 | 7 34139 eem 3 14 0000 0+-0 routine #357 34144 spc , 3000 test tip for set spc 512 34149 set b 0002 34154 lod 8 34226 d226 lod xx in casu 01 34159 spc , 0000 34164 tip , 14 34169 dao9 34169 set b 01 0002 00 2 34174 cmp 4 01 34226 d2s6 34179 lip , 15 3700 3g+0 tf int. prog. trigger 34184 tre l 34219 d219 7 34189 tra i 01 34219 d2/9 error routine 34194 sel 2 0500 34199 wr r 34227 d227 34204 tra i 03 34214 d2a4 34209 tr 1 34219 d219 34214 hlt j 0357 34219 tra i 02 34139 d1l9 34224 tr 1 34239 d239 to next routine 7 2 005 34229 xx357 2 001 34230 | 7 7 routine #358 7 test store spc on tip. 7 spc stored is 7737. preset 7 for bit pickup. 7 34239 eem 3 14 0000 0+-0 34244 spc , 3700 34249 set b 0032 34254 lod 8 34404 d404 reset casu 15 to blanks 34259 rcv u 8888 preset mac-2 34264 sel 2 8888 preset sr 34269 spc , 0014 34274 lfc , 02 34409 d4-9 preset sbr 34279 spc , 0010 34284 lfc , 02 34409 d4-9 preset sbr 7 34289 spc , 7737 34294 tip , 14 34299 dbr9 tip to store spc 34299 lip , 15 3700 3g+0 tf ip trigger 34304 spc , 3710 34309 set b 0008 34314 cmp 4 34417 d417 cmp spc stored equal 7737 34319 spc , 0000 34324 tre l 34359 d359 7 34329 tra i 01 34359 d3v9 error routine 34334 sel 2 0500 34339 wr r 34418 d418 34344 tra i 03 34354 d3e4 34349 tr 1 34359 d359 34354 hlt j 0358 34359 tra i 02 34239 d2l9 34364 tr 1 34429 d429 to next routine 7 2 040 34404 blanks 2 005 34409 +++++ 2 008 34417 00007737 2 003 34420 358 2 001 34421 | 7 7 routine #359 7 test store spc on tip. 7 spc stored is 0000. preset 7 sbr to test for bit pickup. 7 34429 eem 3 14 0000 0+-0 34434 spc , 3700 34439 set b 0032 34444 lod 8 34589 d589 reset casu 15 to blanks 34449 rcv u 0000 preset mac-2 34454 sel 2 0000 preset sr 34459 spc , 0004 34464 lfc , 02 34594 d5r4 34469 spc , 0000 preset sbr 34474 lfc , 02 34594 d5r4 with 77777777 7 34479 tip , 14 34484 ddq4 tip to store spc 34484 lip , 15 3700 3g+0 tf ip trigger 34489 spc , 3710 34494 set b 0008 34499 cmp 4 34602 d602 cmp spc stored equal 0000 34504 spc , 0000 34509 tre l 34544 d544 7 34514 tra i 01 34544 d5u4 error routine 34519 sel 2 0500 34524 wr r 34603 d603 34529 tra i 03 34539 d5c9 34534 tr 1 34544 d544 34539 hlt j 0359 34544 tra i 02 34429 d4k9 34549 tr 1 34614 d614 to next routine 7 2 040 34589 blanks 2 005 34594 77777 2 008 34602 00000000 2 003 34605 359 2 001 34606 | 7 7 routine #360 7 test store mac-2 on tip. 7 max-2 stored is 6666 7 34614 eem 3 14 0000 0+-0 34619 spc , 3700 34624 set b 0000 34629 set b 0028 clear casu 15 to zeros 34634 spc , 0000 34639 rcv u 6666 set mac-2 34644 tip , 14 34649 dfm9 tip to store mac-2 34649 lip , 15 3700 3g+0 lip to tf ip trigger 34654 spc , 3720 34659 set b 0004 34664 cmp 4 34718 d718 cmp mac-2 stored is 6666 34669 spc , 0000 34674 tre l 34709 d709 7 34679 tra i 01 34709 d7 9 error routine 34684 sel 2 0500 34689 wr r 34719 d719 34694 tra i 03 34704 d7+4 34699 tr 1 34709 d709 34704 hlt j 0360 34709 tra i 02 34614 d6j4 34714 tr 1 34729 d729 to next routine 7 2 004 34718 6666 2 003 34721 360 2 001 34722 | 7 34729 eem 3 14 0000 0+-0 routine #361 34734 spc , 3700 test store mac-2 on tip 34739 set b 0000 mac-2 stored is 159999 34744 set b 0032 reset casu 15 34749 spc , 0000 34754 rcv u 159999 i99i set mac-2 34759 tip , 14 34764 dgo4 tip to store mac-2 34764 lip , 15 3700 3g+0 lip to tf ip trigger 34769 spc , 3720 34774 set b 0004 34779 cmp 4 34833 d833 cmp mac-2 stored is i99i 34784 spc , 0000 34789 tre l 34824 d824 7 34794 tra i 01 34824 d8s4 error routine 34799 sel 2 0500 34804 wr r 34834 d834 34809 tra i 03 34819 d8a9 34814 tr 1 34824 d824 34819 hlt j 0361 34824 tra i 02 34729 d7k9 34829 tr 1 34844 d844 to next routine 7 2 004 34833 i99i 2 003 34836 361 2 001 34837 | 7 7 routine #362 7 test store sr on tip. 7 sr stored is 6666 7 34844 eem 3 14 0000 0+-0 34849 spc , 3700 34854 set b 0000 34859 set b 0032 clear casu 15 to zeros 34864 spc , 0000 34869 sel 2 6666 set sr 6666 34874 tip , 14 34879 dhp9 tip to store sr 34879 lip , 15 3700 3g+0 lip to tf ip trigger 34884 spc , 3730 34889 set b 0004 34894 cmp 4 34948 d948 cmp sr stored is 6666 34899 spc , 0000 34904 tre l 34939 d939 7 34909 tra i 01 34939 d9t9 error routine 34914 sel 2 0500 34919 wr r 34949 d949 34924 tra i 03 34934 d9c4 34929 tr 1 34939 d939 34934 hlt j 0362 34939 tra i 02 34844 d8m4 34944 tr 1 34959 d959 7 2 004 34948 6666 2 003 34951 362 2 001 34952 | 7 34959 eem 3 14 0000 0+-0 routine #363 34964 spc , 3700 test store sr on tip 34969 set b 0000 sr stored is 9999 34974 set b 0032 reset casu 15 34979 spc , 0000 34984 sel 2 9999 set sr 34989 tip , 14 34994 dir4 tip to store sr 34994 lip , 15 3700 3g+0 lip to tf ip trigger 34999 spc , 3730 35004 set b 0004 35009 cmp 4 35063 e063 cmp mac-2 stored is i99i 35014 spc , 0000 35019 tre l 35054 e054 7 35024 tra i 01 35054 e0v4 error routine 35029 sel 2 0500 35034 wr r 35064 e064 35039 tra i 03 35049 e0d9 35044 tr 1 35054 e054 35049 hlt j 0363 35054 tra i 02 34959 d9n9 35059 tr 1 35074 e074 to next routine 7 2 004 35063 9999 2 003 35066 363 2 001 35067 | 7 7 routine #364 7 test gen zeros in words 1,2,3 7 of casu 15 on tip. 7 35074 eem 3 14 0000 0+-0 35079 spc , 3700 35084 set b 0032 35089 lod 8 35269 e269 reset casu 15 to blanks 7 35094 spc , 1111 set spc 35099 rcv u 2222 set mac-2 35104 sel 2 6666 set sr 35109 tip , 14 35114 eaj4 tip to gen zeros 35114 lip , 15 3700 3g+0 lip to tf ip trigger 35119 spc , 3714 35124 ufc , 03 35284 e2h4 ufc zeros wd 1 35129 spc , 3724 35134 ufc , 03 35279 e2g9 ufc zeros wd 1 35139 spc , 3734 35144 ufc , 03 35274 e2g4 ufc store marks wd 3 7 35149 sb % 12 35289 eb89 sb to 35154 sb % 12 35288 eb88 make four 35159 sb % 12 35287 eb87 dilroys 35164 sb % 12 35286 eb86 for compare 35169 spc , 0000 35174 set b 0014 35179 lod 8 35299 e299 lod correct field and 35184 cmp 4 35284 e284 compare vs result 35189 tre l 35224 e224 7 35194 tra i 01 35224 e2s4 error routine 35199 sel 2 0500 35204 wr r 35300 e300 35209 tra i 03 35219 e2a9 35214 tr 1 35224 e224 35219 hlt j 0364 35224 tra i 02 35074 e0p4 35229 tr 1 35309 e309 to next routine 7 2 040 35269 blanks 2 015 35284 0000 0000 0000 ufc zeroz field 2 015 35299 ffff 0000 0000 correct result 2 003 35302 364 2 001 35303 | 7 7 routine #365 7 test gen zeros in words 1,2,3 7 of casu 15 on tip. 7 35309 eem 3 14 0000 0+-0 35314 spc , 3700 35319 set b 0032 35324 lod 8 35504 e504 reset casu 15 to blanks 7 35329 spc , 4444 set spc 35334 rcv u 0000 set mac-2 35339 sel 2 8888 set sr 35344 tip , 14 35349 ecm9 tip to generate zeros 35349 lip , 15 3700 3g+0 lip to tf ip trigger 35354 spc , 3714 35359 ufc , 03 35519 e5a9 ufc zeros wd 1 35364 spc , 3724 35369 ufc , 03 35514 e5a4 ufc zeros wd 1 35374 spc , 3734 35379 ufc , 03 35509 e5+9 ufc store marks wd 3 7 35384 sb % 12 35524 ee24 sb to 35389 sb % 12 35523 ee23 make four 35394 sb % 12 35522 ee22 dilroys 35399 sb % 12 35521 ee21 for compare 35404 spc , 0000 35409 set b 0014 35414 lod 8 35534 e534 lod correct field and 35419 cmp 4 35519 e519 compare vs result 35424 tre l 35459 e459 7 35429 tra i 01 35459 e4v9 error routine 35434 sel 2 0500 35439 wr r 35535 e535 35444 tra i 03 35454 e4e4 35449 tr 1 35459 e459 35454 hlt j 0365 35459 tra i 02 35309 e3-9 35464 tr 1 35544 e544 to next routine 7 2 040 35504 blanks 2 015 35519 0000 0000 0000 ufc zeroz field 2 015 35534 ffff 0000 0000 correct result 2 003 35537 365 2 001 35538 | 7 7 routine #366 7 do lip to test set lines. 7 set spc to wr 0000, set mac-2 7 to 0000, set sr to 0000. 7 35544 eem 3 14 0000 0+-0 35549 spc , 3700 35554 set b 0000 35559 set b 0028 set casu 15 all zeros 7 35564 spc , 3333 preset spc 35569 rcv u 6666 preset mac-2 35574 sel 2 9999 preset sr 35579 lip , 15 3700 3g+0 lip to set spc, mac-2, sr 35584 tip , 14 35589 eeq9 tip to store result 35589 lip , 15 3700 3g+0 lip to tf ip. trigger 35594 spc , 3710 35599 cmp 4 35670 e670 cmp spc, mac-2 sr result 35604 spc , 0000 in casu 15 versus zeros 35609 tre l 35644 e644 7 35614 tra i 01 35644 e6u4 error routine 35619 sel 2 0500 35624 wr r 35671 e671 35629 tra i 03 35639 e6c9 35634 tr 1 35644 e644 35639 hlt j 0366 35644 tra i 02 35544 e5m4 35649 tr 1 35679 e679 to next routine 7 2 021 35670 x00000000000000000000 2 003 35673 366 2 001 35674 | 7 7 routine #367 7 test set spc to wr 3313 7 using lip instruction 7 35679 eem 3 14 0000 0+-0 35684 spc , 3710 35689 set b 0020 35694 lod 8 35799 e799 lod casu 15 with spc 3313 35699 spc , 4424 preset spc to 4424 35704 lip , 15 3700 3g+0 lip to set spc to 3313 35709 tip , 14 35714 egj4 tip to store result 35714 lip , 15 3700 3g+0 lip to tf ip. trigger 35719 spc , 3710 35724 set b 0004 35729 cmp 4 35799 e799 cmp spc result 35734 spc , 0000 35739 tre l 35774 e774 7 35744 tra i 01 35774 e7x4 error routine 35749 sel 2 0500 35754 wr r 35800 e800 35759 tra i 03 35769 e7f9 35764 tr 1 35774 e774 35769 hlt j 0367 35774 tra i 02 35679 e6p9 35779 tr 1 35809 e809 7 2 020 35799 00000000000000003313 2 003 35802 367 2 001 35803 | 7 35809 eem 3 14 0000 0+-0 routine #368 35814 spc , 3710 test set spc to wr 35819 set b 0020 4424 on lip 35824 lod 8 35929 e929 lod casu 15 with spc 4424 35829 spc , 4424 preset spc to 4424 35834 lip , 15 3700 3g+0 lip to set spc to 3313 35839 tip , 14 35844 ehm4 tip to store result 35844 lip , 15 3700 3g+0 lip to tf ip. trigger 35849 spc , 3710 35854 set b 0004 35859 cmp 4 35929 e929 cmp spc result 35864 spc , 0000 35869 tre l 35904 e904 7 35874 tra i 01 35904 e9 4 error routine 35879 sel 2 0500 35884 wr r 35930 e930 35889 tra i 03 35899 e8i9 35894 tr 1 35904 e904 35899 hlt j 0368 35904 tra i 02 35809 e8-9 35909 tr 1 35939 e939 to next routine 7 2 020 35929 00000000000000004424 2 003 35932 368 2 001 35933 | 7 7 routine #369 7 test set mac-2 to wr i99i 7 using lip. 7 35939 eem 3 14 0000 0+-0 35944 spc , 3710 35949 set b 0020 35954 lod 8 36059 f059 lod casu 15 with spc i99i 35959 rcv u 6666 preset mac-2 to 6666 35964 lip , 15 3700 3g+0 lip to set spc to 3313 35969 tip , 14 35974 eip4 tip to store result 35974 lip , 15 3700 3g+0 lip to tf ip. trigger 35979 spc , 3720 35984 set b 0004 35989 cmp 4 36051 f051 35994 spc , 0000 35999 tre l 36034 f034 7 36004 tra i 01 36034 f0t4 error routine 36009 sel 2 0500 36014 wr r 36060 f060 36019 tra i 03 36029 f0b9 36024 tr 1 36034 f034 36029 hlt j 0369 36034 tra i 02 35939 e9l9 36039 tr 1 36069 f069 7 2 020 36059 00000000i99i00000000 2 003 36062 369 2 001 36063 | 7 36069 eem 3 14 0000 0+-0 routine #370 36074 spc , 3710 test set mac-2 to wr 36079 set b 0020 6666 on lip 36084 lod 8 36189 f189 lod casu 15 with mac-2 6666 36089 rcv u 159999 i99i preset mac-2 to 159999 36094 lip , 15 3700 3g+0 lip to set mac-2 to 6666 36099 tip , 14 36104 fa-4 tip to store result 36104 lip , 15 3700 3g+0 lip to tf ip. trigger 36109 spc , 3720 36114 set b 0004 36119 cmp 4 36181 f181 36124 spc , 0000 36129 tre l 36164 f164 7 36134 tra i 01 36164 f1w4 error routine 36139 sel 2 0500 36144 wr r 36190 f190 36149 tra i 03 36159 f1e9 36154 tr 1 36164 f164 36159 hlt j 0370 36164 tra i 02 36069 f0o9 36169 tr 1 36199 f199 to next routine 7 2 020 36189 00000000666600000000 2 003 36192 370 2 001 36193 | 7 7 routine #371 7 test set sr to wr 9999 7 on lip 7 36199 eem 3 14 0000 0+-0 36204 spc , 3710 36209 set b 0020 36214 lod 8 36319 f319 lod casu 15 with sr 9999 36219 sel 2 6666 preset sr to 6666 36224 lip , 15 3700 3g+0 lip to set sr. 36229 tip , 14 36234 fbl4 tip to store result 36234 lip , 15 3700 3g+0 lip to tf ip. trigger 36239 spc , 3730 36244 set b 0004 36249 cmp 4 36303 f303 36254 spc , 0000 36259 tre l 36294 f294 7 36264 tra i 01 36294 f2z4 error routine 36269 sel 2 0500 36274 wr r 36320 f320 36279 tra i 03 36289 f2h9 36284 tr 1 36294 f294 36289 hlt j 0371 36294 tra i 02 36199 f1r9 36299 tr 1 36329 f329 7 2 020 36319 99990000000000000000 2 003 36322 371 2 001 36323 | 7 36329 eem 3 14 0000 0+-0 routine #372 36334 spc , 3710 test set sr to wr 6666 36339 set b 0020 on lip. 36344 lod 8 36449 f449 lod casu 15 with sr 6666 36349 sel 2 9999 preset sr to 9999 36354 lip , 15 3700 3g+0 lip to set mac-2 to 6666 36359 tip , 14 36364 fco4 tip to store result 36364 lip , 15 3700 3g+0 lip to tf ip. trigger 36369 spc , 3730 36374 set b 0004 36379 cmp 4 36433 f433 36384 spc , 0000 36389 tre l 36424 f424 7 36394 tra i 01 36424 f4s4 error routine 36399 sel 2 0500 36404 wr r 36450 f450 36409 tra i 03 36419 f4a9 36414 tr 1 36424 f424 36419 hlt j 0372 36424 tra i 02 36329 f3k9 36429 tr 1 36459 f459 to next routine 7 2 020 36449 66660000000000000000 2 003 36452 372 2 001 36453 | 7 7 routine #373 7 test for mac-2 80k off 7 on lip to 705-3 mode. 7 36459 eem 3 14 0000 0+-0 36464 spc , 3700 36469 set b 0028 36474 lod 8 36587 f587 lod ic and status and macii 36479 lip , 15 0009 0++9 lip to set 705-3 mode and try 36484 eem 3 14 0000 0+-0 to set mac-2 80k on- 36489 tip , 14 36494 fdr4 tip to store result 36494 lip , 15 3700 3g+0 lip to tf ip. trigger 36499 spc , 3720 36504 set b 0004 36509 cmp 4 36563 f563 cmp mac-2 result of 40k 36514 spc , 0000 36519 tre l 36554 f554 7 36524 tra i 01 36554 f5v4 error routine 36529 sel 2 0500 36534 wr r 36588 f588 36539 tra i 03 36549 f5d9 36544 tr 1 36554 f554 36549 hlt j 0373 36554 tra i 02 36459 f4n9 36559 tr 1 36599 f599 7 2 024 36583 000-0000000+00000000---- 3 36587 36484 f484 2 003 36590 373 2 001 36591 | 7 7 routine #374 7 test bl set from wr lines 7 to spc,mac-2,sr during lip 7 36599 eem 3 14 0000 0+-0 36604 spc , 3710 36609 set b 0020 lod casu 15 with 8 bits 36614 lod 8 36714 f714 in spc,mac-2 and sr words 36619 lip , 15 3700 3g+0 lip to set spc,mac-2,sr 36624 tip , 14 36629 ffk9 tip to store result 36629 lip , 15 3700 3g+0 lip to tf ip. trigger 36634 spc , 3710 36639 set b 0020 36644 cmp 4 36734 f734 cmp spc,mac-2,sr result 36649 spc , 0000 36654 tre l 36689 f689 7 36659 tra i 01 36689 f6y9 error routine 36664 sel 2 0500 36669 wr r 36735 f735 36674 tra i 03 36684 f6h4 36679 tr 1 36689 f689 36684 hlt j 0374 36689 tra i 02 36599 f5r9 36694 tr 1 36744 f744 to next routine 7 2 020 36714 88880000888800009999 test field 2 020 36734 88880000888800001111 correct result 2 003 36737 374 2 001 36738 | 7 7 routine #375 7 test bl set from wr lines 7 to spc,mac-2, sr during lip. 7 36744 eem 3 14 0000 0+-0 36749 spc , 3710 36754 set b 0020 lod casu 15 with 2 bits 36759 lod 8 36859 f859 in spc, mac-2 and sr words 36764 lip , 15 3700 3g+0 lip to set spc,mac-2,sr 36769 tip , 14 36774 fgp4 tip to store result 36774 lip , 15 3700 3g+0 lip to tf ip. trigger 36779 spc , 3710 36784 set b 0020 36789 cmp 4 36859 f859 cmp spc,mac-2,sr result 36794 spc , 0000 36799 tre l 36834 f834 7 36804 tra i 01 36834 f8t4 error routine 36809 sel 2 0500 36814 wr r 36860 f860 36819 tra i 03 36829 f8b9 36824 tr 1 36834 f834 36829 hlt j 0375 36834 tra i 02 36744 f7m4 36839 tr 1 36869 f869 7 2 020 36859 22220000222200002222 2 003 36862 375 2 001 36863 | 7 7 routine #376 7 test bl set from wr lines 7 to spc,mac-2,sr during lip. 7 36869 eem 3 14 0000 0+-0 36874 spc , 3710 36879 set b 0020 set up 8-2-1 bits in 36884 lod 8 36984 f984 in spc,mac-2 and sr words 36889 lip , 15 3700 3g+0 lip to set spc,mac-2,sr 36894 tip , 14 36899 fhr9 tip to store result 36899 lip , 15 3700 3g+0 lip to tf ip. trigger 36904 spc , 3710 36909 set b 0020 36914 cmp 4 37004 g004 cmp result 36919 spc , 0000 36924 tre l 36959 f959 7 36929 tra i 01 36959 f9v9 error routine 36934 sel 2 0500 36939 wr r 37005 g005 36944 tra i 03 36954 f9e4 36949 tr 1 36959 f959 36954 hlt j 0376 36959 tra i 02 36869 f8o9 36964 tr 1 37014 g014 to next routine 7 2 020 36984 ====0000====0000==== test field 2 020 37004 11110000111100001111 correct result 2 003 37007 376 2 001 37008 | 7 7 routine #377 7 test set to wr routings for 7 bit pick up from mac-1 on lip 7 lip address sets up mac-1. 7 37014 eem 3 14 0000 0+-0 37019 spc , 3700 37024 set b 0028 setup casu 15 with 37029 lod 8 37137 g137 mac-2 equal 6667 37034 lip , 15159998 iiih lip to set mac-2 with mac-1 37039 tip , 14 37044 g+m4 sitting on i99h. then tip to 37044 lip , 15 3700 3g+0 store result anbd lip again 37049 spc , 3720 to tf ip trigger 37054 set b 0004 37059 cmp 4 37121 g121 cmp mac-2 result 37064 spc , 0000 37069 tre l 37104 g104 7 37074 tra i 01 37104 g1 4 error routine 37079 sel 2 0500 37084 wr r 37138 g138 37089 tra i 03 37099 g0i9 37094 tr 1 37104 g104 37099 hlt j 0377 37104 tra i 02 37014 g0j4 37109 tr 1 37149 g149 to next routine 7 2 024 37133 00000000666700000000-+-- 3 37137 37039 g039 2 003 37140 377 2 001 37141 | 7 7 routine #378 7 test set to wr routings for 7 bit pickup from mac-1 on lip 7 lip address sets up mac-1. 7 37149 eem 3 14 0000 0+-0 37154 spc , 3700 37159 set b 0028 setup casu 15 with 37164 lod 8 37282 g282 mac-2 equal i99h 37169 lip , 15 6667 6ff7 lip to set mac-2 with mac-1 37174 tip , 14 37179 gap9 sitting on 6667. then tip to 37179 lip , 15 3700 3g+0 store result anbd lip again 37184 spc , 3720 to tf ip trigger 37189 set b 0004 37194 cmp 4 37266 g266 cmp mac-2 result 37199 spc , 0000 37204 tre l 37239 g239 7 37209 tra i 01 37239 g2t9 error routine 37214 sel 2 0500 37219 wr r 37283 g283 37224 tra i 03 37234 g2c4 37229 tr 1 37239 g239 37234 hlt j 0378 37239 tra i 02 37149 g1m9 37244 rcv u 0306 37249 tr 1 01 0204 02 4 37254 tr 1 37294 g294 to next routine 7 2 024 37278 00000000i99h00000000-+-- 3 37282 37174 g174 2 003 37285 378 2 001 37286 | 7 7 routine #390 7 force early end op on 7 op check to turn on 900 chk. 7 37294 tra i 05 52609 sw r bypass all forced error 37299 nop a 0000 routines if 915 switch on 7 37304 eem 3 14 0000 0+-0 37309 spc , 0000 preset storage 37314 set b 0000 word to zeros 37319 set b 0008 7 37324 lem 3 15 0000 0++0 37329 lfc , 02 37399 g3r9 force op chk 7 37334 nop a 10 37374 glp4 test for false transfer 7 37339 sel 2 0900 test 900 37344 trs o 37354 g354 37349 tr 1 37374 g374 7 37354 set b 0004 37359 cmp 4 37432 g432 test that lfc was 37364 tre l 37374 g374 not completed 37369 tr 1 37409 g409 7 37374 tra i 01 37409 g4 9 error routine 37379 sel 2 0500 37384 wr r 37433 g433 37389 tra i 03 37404 g4+4 37394 tr 1 37409 g409 37399 hlt j 0390 37404 hlt j 0390 37409 tra i 02 37304 g3-4 37414 rcv u 0306 37419 tr 1 01 0204 02 4 37424 tr 1 37444 g444 to next routine 7 7 2 008 37432 00000500 2 005 37437 390 c 2 001 37438 | 7 7 routine #391 7 force dr vrc in char. twO 7 and three to give 900 check. 7 test sel 0900 plus trs 00 7 test trs 10. 7 37444 set b 0002 37449 lod 8 37591 g591 33 37454 sb % 08 37473 gm73 make instructions redundant 37459 sb % 08 37472 gm72 37464 sb % 08 37503 gn03 37469 sb % 08 37502 gn02 7 37474 nop a 0330 force 900 chk 37479 sel 2 0900 37484 trs o 37494 g494 tf 0900 37489 tr 1 37534 g534 37494 trs o 37534 g534 check for 900 off 37499 unl 7 37473 g473 7 37504 nop a 0330 force 900 chk 37509 unl 7 37503 g503 37514 trs o 10 37524 gnk4 tf 900 37519 tr 1 37534 g534 37524 trs o 10 37534 gnl4 check for 900 off 37529 tr 1 37574 g574 7 37534 unl 7 37473 g473 correct redundancies 37539 unl 7 37503 g503 7 37544 tra i 01 37574 g5x4 error routine 37549 sel 2 0500 37554 wr r 37592 g592 37559 tra i 03 37569 g5f9 37564 tr 1 37574 g574 37569 hlt j 0391 37574 tra i 02 37444 g4m4 37579 rcv u 0306 37584 tr 1 01 0204 02 4 37589 tr 1 37604 g604 to next routine 7 7 2 002 37591 33 2 005 37596 391 c 2 001 37597 | 7 7 routine #392 7 force 4/9 check with indirect 7 address to give 900 check. 7 in 7080 and 705-3 modes. 7 37604 eem 3 14 0000 0+-0 7080 mode 37609 eia , 10 0000 0--0 37614 nop a 37623 g623 force 4/9 chk 37619 nop a 0000 37624 nop a 0000 37629 trs o 10 37639 gol9 37634 tr 1 37669 g669 7 37639 lem 3 15 0000 0++0 705-3 mode 37644 sb % 13 37649 gfu9 make the nop address indirect 37649 nop a 37658 g658 force 4/9 chk 37654 nop a 0000 37659 nop a 0000 37664 trs o 10 37699 gor9 7 37669 tra i 01 37699 g6z9 error routine 37674 sel 2 0500 37679 wr r 37715 g715 37684 tra i 03 37694 g6i4 37689 tr 1 37699 g699 37694 hlt j 0392 37699 tra i 02 37604 g6-4 37704 rcv u 0306 37709 tr 1 01 0204 02 4 37714 tr 1 37729 g729 to next routine 7 7 2 005 37719 392 c 2 001 37720 | 7 7 routine #393 7 force 4/9 check to give 7 900 check on the transfer, 7 tr, trs, tra, tre 7 37729 tr 1 37733 g733 4/9 chk on tr 37734 nop a 0000 37739 trs o 10 37749 gpm9 37744 tr 1 37809 g809 7 37749 sel 2 0000 37754 trs o 37758 g758 4/9 chk on trs 37759 nop a 0000 37764 trs o 10 37774 gpp4 37769 tr 1 37809 g809 7 37774 tra i 37778 g778 4/9 chk on tra 37779 nop a 0000 37784 trs o 10 37794 gpr4 37789 tr 1 37809 g809 7 37794 tre l 37798 g798 4/9 chk on tre 37799 nop a 0000 37804 trs o 10 37839 gql9 7 37809 tra i 01 37839 g8t9 error routine 37814 sel 2 0500 37819 wr r 37855 g855 37824 tra i 03 37834 g8c4 37829 tr 1 37839 g839 37834 hlt j 0393 37839 tra i 02 37729 g7k9 37844 rcv u 0306 37849 tr 1 01 0204 02 4 37854 tr 1 37869 g869 to next routine 7 7 2 005 37859 393 c 2 001 37860 | 7 7 routine #394 7 force 4/9 check to give 7 900 check on the transfer, 7 trh, trz, trp, tzb 7 37869 trh k 37873 g873 4/9 chk on trh 37874 nop a 0000 37879 trs o 10 37889 gqq9 37884 tr 1 37949 g949 7 37889 trz n 37893 g893 4/9 chk on trz 37894 nop a 0000 37899 trs o 10 37909 gr-9 37904 tr 1 37949 g949 7 37909 trp m 37913 g913 4/9 chk on trp 37914 nop a 0000 37919 trs o 10 37929 grk9 37924 tr 1 37949 g949 7 37929 rcv u 0060 37934 tzb . 05 37938 gzt8 4/9 chk on tzb 37939 nop a 0000 37944 trs o 10 37979 grp9 7 37949 tra i 01 37979 g9x9 error routine 37954 sel 2 0500 37959 wr r 37995 g995 37964 tra i 03 37974 g9g4 37969 tr 1 37979 g979 37974 hlt j 0394 37979 tra i 02 37869 g8o9 37984 rcv u 0306 37989 tr 1 01 0204 02 4 37994 tr 1 38009 h009 to next routine 7 7 2 005 37999 394 c 2 001 38000 | 7 7 routine #395 7 force 4/9 check to give 7 900 check on ntr and tip. 7 38009 eem 3 14 0000 0+-0 38014 spc , 0000 38019 set b 0000 38024 ntr x 38028 h028 4/9 chk on ntr 38029 nop a 0000 38034 trs o 10 38044 h-m4 38039 tr 1 38114 h114 7 38044 tip , 14 38048 h+m8 4/9 chk on tip 38049 nop a 0000 38054 trs o 10 38064 h-o4 38059 tr 1 38089 h089 7 38064 spc , 3700 reset casu 15 on good 38069 set b 0008 38074 lod 8 38174 h174 38079 set b 0032 38084 lip , 15 0009 0++9 7 38089 spc , 3700 reset casu 15 on good 38094 set b 0008 38099 lod 8 38184 h184 38104 set b 0032 38109 lip , 15 0009 0++9 7 38114 tra i 01 38144 h1u4 error routine 38119 sel 2 0500 38124 wr r 38160 h160 38129 tra i 03 38139 h1c9 38134 tr 1 38144 h144 38139 hlt j 0395 38144 tra i 02 38009 h0-9 38149 rcv u 0306 38154 tr 1 01 0204 02 4 38159 tr 1 38189 h189 to next routine 7 2 005 38164 395 c 2 001 38165 | 2 005 38170 0-+-- location for lip -good 3 38174 38144 h144 2 006 38180 00-+-- location for lip -error 3 38184 38114 h114 7 7 routine #396 7 force 4/9 check to give 7 900 check on tmt 00 + snd . also 7 force 9 chk to give 900 chk 7 on tct operation 7 38189 rcv u 38319 h319 38194 tmt 9 38313 h313 force 4/9 chk on tmt 00 38199 trs o 10 38209 hk-9 38204 tr 1 38264 h264 7 38209 set B 0000 38214 rcv u 38319 h319 38219 snd / 38313 h313 force 4/9 chk on snd 38224 trs o 10 38234 hkl4 38229 tr 1 38264 h264 7 38234 set B 0004 force 9 chk on tct 38239 lod 8 38314 h314 38244 unl 7 79959 i95r 38249 rcv u 79989 i98r 38254 tct , 08 79958 ir5q 38259 trs o 10 38294 hkr4 7 38264 tra i 01 38294 h2z4 error routine 38269 sel 2 0500 38274 wr r 38325 h325 38279 tra i 03 38289 h2h9 38284 tr 1 38294 h294 38289 hlt j 0396 38294 tra i 02 38189 h1q9 38299 rcv u 0306 38304 tr 1 01 0204 02 4 38309 tr 1 38339 h339 to next routine 7 2 001 38310 # 2 001 38311 # 2 001 38312 # 2 001 38313 # 2 001 38314 # 2 005 38324 395 c 2 001 38330 | 7 7 routine #397 7 force 4/9 check to give 7 900 check on operations 7 lda, ula, and aam. 7 38339 lda = 38428 h428 38344 trs o 10 38354 hln4 4/9 chk on lda 38349 tr 1 38379 h379 7 38354 ula * 38433 h433 4/9 chk on ula 38359 trs o 10 38369 hlo9 38364 tr 1 38379 h379 7 38369 aam @ 38433 h433 38374 trs o 10 38409 hm-9 7 38379 tra i 01 38409 h4 9 error routine 38384 sel 2 0500 38389 wr r 38435 h435 38394 tra i 03 38404 h4+4 38399 tr 1 38409 h409 38404 hlt j 0397 38409 tra i 02 38339 h3l9 38414 rcv u 0306 38419 tr 1 01 0204 02 4 38424 tr 1 38449 h449 to next routine 7 2 005 38429 00000 2 005 38434 00000 2 005 38439 397 c 2 001 38440 | 7 7 routine #398 7 force 4/9 check to give 7 900 check in i/a time on the 7 second address. 7 test dr char. zero vrc 7 blocked in i/a time. 7 38449 lem 3 15 0000 0++0 38454 sb % 13 38459 hdv9 make the nop address indirect 38459 tr 1 38464 h464 4/9 chk in i/a time 38464 nop a 38468 h468 38469 nop a 0000 38474 trs o 10 38484 hmq4 38479 tr 1 38529 h529 7 38484 set b 0001 38489 lod 8 38575 h575 38494 sb % 13 38509 he 9 make the nop address indirect 38499 nop a 0000 38504 sb % 08 38495 hm95 38509 nop a 38499 h499 no 4/9 check in i/a time 38514 unl 7 38495 h495 38519 trs o 10 38529 hnk9 38524 tr 1 38559 h559 7 38529 tra i 01 38559 h5v9 error routine 38534 sel 2 0500 38539 wr r 38576 h576 38544 tra i 03 38554 h5e4 38549 tr 1 38559 h559 38554 hlt j 0398 38559 tra i 02 38449 h4m9 38564 rcv u 0306 38569 tr 1 01 0204 02 4 38574 tr 1 38589 h589 to next routine 7 2 001 38575 A 2 005 38580 398 c 2 001 38581 | 7 7 routine #399 7 force op check to give 900 7 check on ampersand, zero, 7 lozenge and group mark. 7 38589 + + 0000 op chk on + 38594 trs o 10 38604 ho-4 38599 tr 1 38649 h649 7 38604 0 0 0000 op chk on zero 38609 trs o 10 38619 hoj9 38614 tr 1 38649 h649 7 38619 | | 0000 op chk on | (g.m) 38624 trs o 10 38634 hol4 38629 tr 1 38649 h649 7 38634 sb % 12 38635 hf35 make g a gm 38639 add g 0000 op chk on group make 38644 trs o 10 38679 hop9 7 38649 tra i 01 38679 h6x9 error routine 38654 sel 2 0500 38659 wr r 38695 h695 38664 tra i 03 38674 h6g4 38669 tr 1 38679 h679 38674 hlt j 0399 38679 tra i 02 38589 h5q9 38684 rcv u 0306 38689 tr 1 01 0204 02 4 38694 tr 1 38709 h709 to next routine 7 2 005 38699 399 c 2 001 38700 | 7 7 routine #400 7 test char 4 of dr vrc 7 using 900 check. bits are, 7 -1- , -cba42- , 7 -ca821- and -b84- 7 38709 eem 3 14 0000 0+-0 38714 set b 0001 38719 lod 8 38880 h880 38724 sb % 08 38729 hp29 38729 nop a 0001 dr vrc on -1- bit 38734 unl 7 38729 h729 38739 trs o 10 38749 hpm9 38744 tr 1 38834 h834 7 38749 lod 8 38881 h881 38754 sb % 08 38759 hp59 38759 nop a 000f dr vrc on -CBa42- bits 38764 unl 7 38729 h729 38769 trs o 10 38779 hpp9 38774 tr 1 38834 h834 7 38779 lod 8 38882 h882 38784 sb % 08 38789 hp89 38789 nop a 000, dr vrc on -CBa821- bits 38794 unl 7 38789 h789 38799 trs o 10 38809 hq-9 38804 tr 1 38834 h834 7 38809 lod 8 38883 h883 38814 sb % 08 38819 hq19 38819 nop a 000* dr vrc on -b84-bits 38824 unl 7 38819 h819 38829 trs o 10 38864 hqo4 7 38834 tra i 01 38864 h8w4 error routine 38839 sel 2 0500 38844 wr r 38884 h884 38849 tra i 03 38859 h8e9 38854 tr 1 38864 h864 38859 hlt j 0400 38864 tra i 02 38709 h7-9 38869 rcv u 0306 38874 tr 1 01 0204 02 4 38879 tr 1 38894 h894 to next routine 7 2 004 38883 1f.* 2 005 38888 400 c 2 001 38889 | 7 7 routine #401 7 test char 3 of dr vrc 7 using 900 check. bits are, 7 -1- , -cba42- , 7 -ca821- and -b84- 7 38894 eem 3 14 0000 0+-0 38899 set b 0001 38904 lod 8 39065 i065 38909 sb % 08 38913 hr13 38914 nop a 0010 dr vrc on -1- bit 38919 unl 7 38913 h913 38924 trs o 10 38934 hrl4 38929 tr 1 39019 i019 7 38934 lod 8 39066 i066 38939 sb % 08 38943 hr43 38944 nop a 00f0 dr vrc on -CBa42- bits 38949 unl 7 38943 h943 38954 trs o 10 38964 hro4 38959 tr 1 39019 i019 7 38964 lod 8 39067 i067 38969 sb % 08 38973 hr73 38974 nop a 00,0 dr vrc on -CBa821- bits 38979 unl 7 38973 h973 38984 trs o 10 38994 hrr4 38989 tr 1 39019 i019 7 38994 lod 8 39068 i068 38999 sb % 08 39003 i-03 39004 nop a 00*0 dr vrc on -b84-bits 39009 unl 7 39003 i003 39014 trs o 10 39049 i-m9 7 39019 tra i 01 39049 i0u9 error routine 39024 sel 2 0500 39029 wr r 39069 i069 39034 tra i 03 39044 i0d4 39039 tr 1 39049 i049 39044 hlt j 0401 39049 tra i 02 38894 h8r4 39054 rcv u 0306 39059 tr 1 01 0204 02 4 39064 tr 1 39079 i079 to next routine 7 2 004 39068 1f,* 2 005 39073 401 c 2 001 39074 | 7 7 routine #402 7 test char 2 of dr vrc 7 using 900 check. bits are, 7 -1- , -cba42- , 7 -ca821- and -b84- 7 39079 eem 3 14 0000 0+-0 39084 set b 0001 39089 lod 8 39250 i250 39094 sb % 08 39097 i-97 39099 nop a 0100 dr vrc on -1- bit 39104 unl 7 39097 i097 39109 trs o 10 39119 ijj9 39114 tr 1 39204 i204 7 39119 lod 8 39251 i251 39124 sb % 08 39127 ij27 39129 nop a 0f00 dr vrc on -CBa42- bits 39134 unl 7 39127 i127 39139 trs o 10 39149 ijm9 39144 tr 1 39204 i204 7 39149 lod 8 39252 i252 39154 sb % 08 39157 ij57 39159 nop a 0,00 dr vrc on -CBa821- bits 39164 unl 7 39157 i157 39169 trs o 10 39179 ijp9 39174 tr 1 39204 i204 7 39179 lod 8 39253 i253 39184 sb % 08 39187 ij87 39189 nop a 0*00 dr vrc on -b84-bits 39194 unl 7 39187 i187 39199 trs o 10 39234 ikl4 7 39204 tra i 01 39234 i2t4 error routine 39209 sel 2 0500 39214 wr r 39254 i254 39219 tra i 03 39229 i2b9 39224 tr 1 39234 i234 39229 hlt j 0402 39234 tra i 02 39079 i0p9 39239 rcv u 0306 39244 tr 1 01 0204 02 4 39249 tr 1 39264 i264 to next routine 7 2 004 39253 1f,* 2 005 39258 402 c 2 001 39259 | 7 7 routine #403 7 test char 1 of dr vrc 7 using 900 check. bits are, 7 -1- , -cba42- , 7 -ca821- and -b84- 7 39264 eem 3 14 0000 0+-0 39269 set b 0001 39274 lod 8 39435 i435 39279 sb % 08 39281 ik81 39284 nop a 1000 dr vrc on -1- bit 39289 unl 7 39281 i281 39294 trs o 10 39304 il-4 39299 tr 1 39389 i389 7 39304 lod 8 39436 i436 39309 sb % 08 39311 il11 39314 nop a 30000 +000 dr vrc on -CBa42- bits 39319 unl 7 39311 i311 39324 trs o 10 39334 ill4 39329 tr 1 39389 i389 7 39334 lod 8 39437 i437 39339 sb % 08 39341 il41 39344 nop a 3=000 ,000 dr vrc on -CBa821- bits 39349 unl 7 39341 i341 39354 trs o 10 39364 ilo4 39359 tr 1 39389 i389 7 39364 lod 8 39438 i438 39369 sb % 08 39371 il71 39374 nop a 2@000 *000 dr vrc on -b84-bits 39379 unl 7 39371 i371 39384 trs o 10 39419 imj9 7 39389 tra i 01 39419 i4/9 error routine 39394 sel 2 0500 39399 wr r 39439 i439 39404 tra i 03 39414 i4a4 39409 tr 1 39419 i419 39414 hlt j 0403 39419 tra i 02 39264 i2o4 39424 rcv u 0306 39429 tr 1 01 0204 02 4 39434 tr 1 39449 i449 to next routine 7 2 004 39438 1f,* 2 005 39443 403 c 2 001 39444 | 7 7 routine #404 7 test char 0 of dr vrc 7 using 900 check. bits are, 7 -1- , -cba42- , 7 -ca821- and -b84- 7 39449 eem 3 14 0000 0+-0 39454 set b 0001 39459 lod 8 39631 i631 39464 sb % 08 39465 im65 39469 tr 1 39474 i474 dr vrc on -1- bit 39474 unl 7 39465 i465 39479 trs o 10 39489 imq9 39484 tr 1 39579 i579 7 39489 lod 8 39632 i632 39494 sb % 08 39495 im95 39499 st f 39643 i643 dr vrc on -CBa42- bits 39504 unl 7 39495 i495 39509 trs o 10 39519 inj9 39514 tr 1 39579 i579 7 39519 lod 8 39633 i633 39524 sb % 08 39525 in25 39529 cno , 11 0000 0-+0 dr vrc on -CBa821- bits 39534 unl 7 39525 i525 39539 trs o 10 39549 inm9 39544 tr 1 39579 i579 7 39549 rad h 01 39640 i6u0 39554 lod 8 39634 i634 39559 sb % 08 39560 in60 39564 ula * 01 39649 i6u9 dr vrc on -b84-bits 39569 unl 7 39560 i560 39574 trs o 10 39609 io-9 7 39579 tra i 01 39609 i6 9 error routine 39584 sel 2 0500 39589 wr r 39625 i625 39594 tra i 03 39604 i6+4 39599 tr 1 39609 i609 39604 hlt j 0404 39609 tra i 02 39449 i4m9 39614 rcv u 0306 39619 tr 1 01 0204 02 4 39624 tr 1 39654 i654 to next routine 7 2 005 39629 404 c 2 001 39630 | 2 004 39634 1f,* 2 006 39640 x0000+ 2 009 39649 x00x00000 7 7 routine #405 7 a. routine sbr to stor with 900 7 trigger on and test stor 7 char 5 for bit pick up. 7 b. route trs, not ssr 0000 7 and test for false tf of 7 900 tgr. 7 39654 eem 3 14 0000 0+-0 39659 spc , 0005 39664 set b 0000 39669 set b 0001 39674 tr 1 39678 i678 900 tgr on 39679 lod 8 39755 i755 0 39684 trs o 11 39689 ioh9 39689 trs o 10 39699 ior9 test 900 trg on 39694 tr 1 39709 i709 7 39699 cmp 4 39755 i755 vs 0 39704 tre l 39739 i739 7 39709 tra i 01 39739 i7t9 error routine 39714 sel 2 0500 39719 wr r 39756 i756 39724 tra i 03 39734 i7c4 39729 tr 1 39739 i739 39734 hlt j 0405 39739 tra i 02 39654 i6n4 39744 rcv u 0306 39749 tr 1 01 0204 02 4 39754 tr 1 39769 i769 to next routine 7 2 001 39755 0 2 005 39760 405 c 2 001 39761 | 7 7 routine #406 7 force 901 check using sb 08. 7 test for false turn off of 901 7 and for correct trs 11 to turn 7 off 901 7 39769 sb % 08 39819 iq19 make redundancy 39774 sb % 08 39819 iq19 correct red. and force 901 7 39779 trs o 10 39809 iq-9 39784 sel 2 0901 39789 trs o 39799 i799 test 901 39794 tr 1 39809 i809 39799 trs o 39809 i809 test 901 off 39804 tr 1 39854 i854 7 39809 sb % 09 39819 iq/9 safety reset if error 39814 trs o 11 39819 iqa9 39819 nop a 7777 7 39824 tra i 01 39854 i8v4 error routine 39829 sel 2 0500 39834 wr r 39870 i870 39839 tra i 03 39849 i8d9 39844 tr 1 39854 i854 39849 hlt j 0406 39854 tra i 02 39769 i7o9 39859 rcv u 0306 39864 tr 1 01 0204 02 4 39869 tr 1 39884 i884 to next routine 7 2 005 39874 406 c 2 001 39875 | 7 7 routine #407 7 force 901 check via add 7 trigger using sb 09. test 7 for false and proper turn 7 off of 901 7 39884 sb % 08 39819 iq19 make redundancy 39889 sb % 08 39819 iq19 correct red. and force 901 7 39894 nop a 11 39929 irb9 test for 39899 sel 2 0000 false transfer 39904 trs o 39929 i929 or turn off 7 39909 trs o 11 39919 ira9 test 901 39914 tr 1 39929 i929 39919 trs o 11 39929 irb9 test 901 off 39924 tr 1 39959 i959 7 39929 tra i 01 39959 i9v9 error routine 39934 sel 2 0500 39939 wr r 39976 i976 39944 tra i 03 39954 i9e4 39949 tr 1 39959 i959 39954 hlt j 0407 39959 tra i 02 39884 i8q4 39964 rcv u 0306 39969 tr 1 01 0204 02 4 39974 tr 1 005m to next routine 7 2 001 39975 7 2 005 39980 407 c 2 001 39981 | 7 7 routine #408 7 test mbr code check using tzb 7 a. with 1 bit 7 b. with cba 42 bits 7 c. with c a8 21 bits 7 40054 set b 0003 pick up reset 40059 lod 8 40209 020r 7 40064 sb % 08 40202 0k0k 40069 rcv u 40202 020k 40074 tzb . 01 40079 00xr 901 chk on 1 bit 40079 trs o 11 40089 0-hr 40084 tr 1 40134 013m 7 40089 sb % 08 40203 0k0l 40094 rcv u 40203 020l 40099 tzb . 01 40104 01 m 901 chk on cba 42 bits 40104 trs o 11 40114 0jam 40109 tr 1 40134 013m 7 40114 sb % 08 40204 0k0m 40119 rcv u 40204 020m 40124 tzb . 01 40129 01sr 901 chk on c a8 21 bits 40129 trs o 11 40144 0jdm 7 40134 unl 7 40204 020m error reset 40139 tr 1 40154 015m 7 40144 unl 7 40204 020m reset 40149 tr 1 40184 018m 7 40154 tra i 01 40184 01ym error routine 40159 sel 2 0500 40164 wr r 40210 021- 40169 tra i 03 40179 01gr 40174 tr 1 40184 018m 40179 hlt j 0408 40184 tra i 02 40054 00nm 40189 rcv u 0306 40194 tr 1 01 00204 02 4 40199 tr 1 40224 022m to next routine 7 2 005 40204 --1f, for sb 08 2 005 40209 --1f, for reset 2 005 40214 408 c 2 001 40215 | 7 7 routine #409 7 test mbr code check using tzb 7 a. with b 84 bits 7 b. with storage mark 7 40224 set b 0002 40229 lod 8 40348 034q 7 40234 sb % 08 40346 0l4o 40239 rcv u 40346 034o 40244 tzb . 01 40249 02ur 40249 trs o 11 40259 0ker 40254 tr 1 40279 027r 7 40259 sb % 01 40345 03un 40264 rcv u 40345 034n 40269 tzb . 01 40274 02xm 40274 trs o 11 40289 0khr 7 40279 unl 7 40346 034o error reset 40284 tr 1 40299 029r 7 40289 unl 7 40346 034o reset 40294 tr 1 40329 032r 7 40299 tra i 01 40329 03sr error routine 40304 sel 2 0500 40309 wr r 40349 034r 40314 tra i 03 40324 03bm 40319 tr 1 40329 032r 40324 hlt j 0409 40329 tra i 02 40224 02km 40334 rcv u 0306 40339 tr 1 01 00204 02 4 40344 tr 1 40359 035r to next routine 7 2 002 40346 1* for sb 08 and sb 01 2 002 40348 1* reset 2 005 40353 409 c 2 001 40354 | 7 7 routine #410 7 force 901 check through sbr 7 vcr using set instruction. 7 three redundant characters 7 in storage. 7 40359 eem 3 14 00000 0+-0 40364 sb % 08 40488 0m8q make three 40369 sb % 08 40486 0m8o redundant 40374 sb % 08 40485 0m8n characters 7 40379 spc , 0000 40384 set b 0004 40389 lod 8 40488 048q 40394 trs o 11 40399 0lir 7 40399 set b 0004 40404 trs o 11 40424 0mbm test 901 7 40409 lod 8 40492 049k error reset 40414 unl 7 40488 048q 40419 tr 1 40439 043r 7 40424 lod 8 40492 049k reset 40429 unl 7 40488 048q 40434 tr 1 40469 046r 7 40439 tra i 01 40469 04wr error routine 40444 sel 2 0500 40449 wr r 40493 049l 40454 tra i 03 40464 04fm 40459 tr 1 40469 046r 40464 hlt j 0410 40469 tra i 02 40359 03nr 40474 rcv u 0306 40479 tr 1 01 00204 02 4 40484 tr 1 40504 050m to next routine 7 3 40488 40394 039m 3 40492 40394 039m 2 005 40497 410 c 2 001 40498 | 7 7 routine #411 7 A. test for false 901 when 7 wr is redundant 7 b. test for bit pickup in 7 storage char 5 when 7 901 check is on. 7 40504 eem 3 14 00000 0+-0 40509 sb % 08 40626 0o2o 40514 spc , 0005 store char 5 40519 set b 0001 40524 lod 8 40626 062o 40529 trs o 11 40534 0ncm tf 901 40534 nop a 0000 40539 trs o 11 40569 0nfr test for false 901 7 40544 sb % 09 40626 0oso correct redundancy 40549 lod 8 40628 062q 40554 trs o 11 40559 0ner tf 901 40559 cmp 4 40628 062q test for bit pickup in char 5 40564 tre l 40609 060r 7 40569 sb % 09 40626 0oso error reset 40574 trs o 11 40579 0ngr 7 40579 tra i 01 40609 06 r error routine 40584 sel 2 0500 40589 wr r 40629 062r 40594 tra i 03 40604 06+m 40599 tr 1 40609 060r 40604 hlt j 0411 40609 tra i 02 40359 03nr 40614 rcv u 0306 40619 tr 1 01 00204 02 4 40624 tr 1 40639 063r to next routine 7 2 002 40626 -1 2 002 40628 -1 2 005 40633 411 c 2 001 40634 | 7 7 routine #412 7 test sbr vrc using set l. 7 a. with 1 bit 7 b. with cba 42 bits 7 c. with c a8 21 bits 7 d. with b 84 bits. 7 40639 set b 0001 a 40644 sb % 08 40841 0q4j 40649 lod 8 40841 084j 40654 sb % 09 40841 0quj 40659 trs o 11 40664 0ofm tf 901 40664 set b 0001 40669 trs o 11 40679 0ogr test 901 40674 tr 1 40784 078m 7 40679 sb % 08 40842 0q4k b 40684 lod 8 40842 084k 40689 sb % 09 40842 0quk 40694 trs o 11 40699 0oir tf 901 40699 set b 0001 40704 trs o 11 40714 0pam test 901 40709 tr 1 40784 078m 7 40714 sb % 08 40843 0q4l c 40719 lod 8 40843 084l 40724 sb % 09 40843 0qul 40729 trs o 11 40734 0pcm tf 901 40734 set b 0001 40739 trs o 11 40749 0pdr test 901 40744 tr 1 40784 078m 7 40749 sb % 08 40844 0q4m d 40754 lod 8 40844 084m 40759 sb % 09 40844 0qum 40764 trs o 11 40769 0pfr tf 901 40769 set b 0001 40774 lod 8 40840 084- 40779 trs o 11 40824 0qbm test 901 7 40784 lod 8 40840 084- 40789 trs o 11 40794 0pim 7 40794 tra i 01 40824 08sm error routine 40799 Sel 2 0500 40804 wr r 40845 084n 40809 tra i 03 40819 08ar 40814 tr 1 40824 082m 40819 hlt j 0412 40824 tra i 02 40639 06lr 40829 rcv u 0306 40834 tr 1 01 00204 02 4 40839 tr 1 40859 085r to next routine 7 2 005 40844 -1f.* 2 005 40849 412 c 2 001 40850 | 7 7 routine #413 7 force 901 check through 7 rr vrc using store. 7 four redundant char. 7 40859 set b 0004 40864 lod 8 40938 093q force rr vrC 40869 st f 40934 093m 40874 unl 7 40934 093m 40879 trs o 11 40914 0ram tf 901 7 40884 tra i 01 40914 09/m error routine 40889 Sel 2 0500 40894 wr r 40939 093r 40899 tra i 03 40909 09+r 40904 tr 1 40914 091m 40909 hlt j 0413 40914 tra i 02 40859 08nr 40919 rcv u 0306 40924 tr 1 01 00204 02 4 40929 tr 1 40949 094r to next routine 7 2 005 40934 ------ 2 004 40938 z0. 2 005 40943 413 c 2 001 40944 | 7 7 routine #414 7 test rr vrc using store 7 a. c 8 1 bits 7 b. c 42 bits 7 c. 8 21 bits 7 d. c 84 bits 7 40949 set b 0002 A 40954 lod 8 41099 109r 40959 st f 41097 109p 901 on c-8-1 bits 40964 unl 7 41096 109o 40969 trs o 11 40979 0rgr 40974 tr 1 41049 104r 7 40979 lod 8 41101 110j B 40984 st f 41097 109p 901 on c-4-2 bits 40989 unl 7 41096 109o 40994 trs o 11 41004 1-+m 40999 tr 1 41049 104r 7 41004 lod 8 41103 110l c 41009 st f 41097 109p 901 on 8-2-1 bits 41014 unl 7 41096 109o 41019 trs o 11 41029 1-br 41024 tr 1 41049 104r 7 41029 lod 8 41105 110n d 41034 st f 41097 109p 901 on c-8-4 bits 41039 unl 7 41096 109o 41044 trs o 11 41079 1-gr 7 41049 tra i 01 41079 10xr error routine 41054 Sel 2 0500 41059 wr r 41106 110o 41064 tra i 03 41074 10gm 41069 tr 1 41079 107r 41074 hlt j 0414 41079 tra i 02 40949 09mr 41084 rcv u 0306 41089 tr 1 01 00204 02 4 41094 tr 1 41119 111r to next routine 7 2 003 41097 --- 2 008 41105 z101.1*1 2 005 41110 414 c 2 001 41111 | 7 7 routine #415 7 a. test dr vrc to 901 check 7 during snd operation 7 b. test pr vrc to 901 check 7 during tmt 00 operation. 7 41119 sb % 08 41267 1k6p 41124 sb % 08 41266 1k6o 41129 set b 0001 41134 rcv u 41274 127m 41139 snd / 41269 126r dr chk on snd 41144 trs o 11 41154 1jem 41149 tr 1 41169 116r 7 41154 rcv u 41274 127m 41159 tmt 9 41269 126r dr chk on tmt 41164 trs o 11 41194 1jim 7 41169 set b 0005 error reset 41174 lod 8 41279 127r 41179 unl 7 41269 126r 41184 unl 7 41274 127m 41189 tr 1 41219 121r 7 41194 set b 0005 reset 41199 lod 8 41279 127r 41204 unl 7 41269 126r 41209 unl 7 41274 127m 41214 tr 1 41249 124r 7 41219 tra i 01 41249 12ur error routine 41224 Sel 2 0500 41229 wr r 41280 128- 41234 tra i 03 41244 12dm 41239 tr 1 41249 124r 41244 hlt j 0415 41249 tra i 02 41119 11jr 41254 rcv u 0306 41259 tr 1 01 00204 02 4 41264 tr 1 41294 129m to next routine 7 2 004 41268 -24- snd/tmt field 2 001 41269 # 2 005 41274 ----- rcv field 2 004 41278 -24- reset 2 001 41279 # 2 005 41284 415 c 2 001 41285 | 7 7 routine #416 7 test dr vrc to 901 check 7 during tct operation 7 41294 eem 3 14 00000 0+-0 41299 set b 0010 41304 lod 8 41424 142m set up 10 character 41309 unl 7 79959 i95r tct field at 79959 41314 sb % 08 79951 ir5j char. 1 of tct field redundant 7 41319 rcv u 79959 i95r 41324 tct , 08 79959 ir5r force 910 chk 41329 unl 7 79959 i95r correct redundancy 41334 trs o 11 41344 1ldm 41339 tr 1 41369 136r 7 41344 sb % 08 79956 ir5o char. 6 of tct field redundant 41349 rcv u 79959 i95r 41354 tct , 08 79959 ir5r force 901 check 41359 unl 7 79959 i95r correct redundancy 41364 trs o 11 41399 1lir 7 41369 tra i 01 41399 13zr error routine 41374 Sel 2 0500 41379 wr r 41425 142n 41384 tra i 03 41394 13im 41389 tr 1 41399 139r 41394 hlt j 0416 41399 tra i 02 41294 12rm 41404 rcv u 0306 41409 tr 1 01 00204 02 4 41414 tr 1 41439 143r to next routine 7 2 009 41423 000000000 2 001 41424 # 2 005 41429 416 c 2 001 41430 | 7 7 routine #417 7 a. step mac i through a 7 memory quadrant and 7 test dr vrc on rww-snd 7 operation 7 b. test dr vrc on tmt 00 7 preceeded by rww 7 41439 set b 0010 41444 lod 8 41574 157m 41449 unl 7 19999 z999 41454 sb % 08 19993 zr93 41459 sb % 08 19992 zr92 41464 set b 01 00000 00 0 place stor. mark in sbr 41469 rww s 0004 step mac i through 20k to given 41474 snd / 0004 dr chk on snd-chk mem. 41479 trs o 11 41489 1mhr 41484 tr 1 41514 151m 7 41489 rww s 19994 z994 41494 tmt 9 19994 z994 dr chk on tmt 41499 snd / 19999 z999 41504 unl 7 19999 z999 reset 41509 trs o 11 41549 1ndr 7 41514 unl 7 19999 z999 reset 41519 tra i 01 41549 15ur error routine 41524 Sel 2 0500 41529 wr r 41575 157n 41534 tra i 03 41544 15dm 41539 tr 1 41549 154r 41544 hlt j 0417 41549 tra i 02 41439 14lr 41554 rcv u 0306 41559 tr 1 01 00204 02 4 41564 tr 1 41589 158r to next routine 7 2 004 41568 1234 2 001 41569 # 2 005 41574 ----- 2 005 41579 417 c 2 001 41580 | 7 7 routine #418 7 test dr vrc all characters 7 on no bit character--sm 7 use snd operation 7 41589 set b 0001 41594 lod 8 41795 179n 41599 sb % 01 41794 17zm 41604 rcv u 41794 179m 41609 snd / 41794 179m dr vrc on char 4 41614 unl 7 41794 179m 41619 trs o 11 41629 1obr 41624 tr 1 41744 174m 7 41629 sb % 01 41793 17zl 41634 rcv u 41794 179m 41639 snd / 41794 179m dr vrc on char 3 41644 unl 7 41793 179l 41649 trs o 11 41659 1oer 41654 tr 1 41744 174m 7 41659 sb % 01 41792 17zk 41664 rcv u 41794 179m 41669 snd / 41794 179m dr vrc on char 2 41674 unl 7 41792 179k 41679 trs o 11 41689 1ohr 41684 tr 1 41744 174m 7 41689 sb % 01 41791 17zj 41694 rcv u 41794 179m 41699 snd / 41794 179m dr vrc on char 1 41704 unl 7 41791 179j 41709 trs o 11 41719 1par 41714 tr 1 41744 174m 7 41719 sb % 01 41790 17z- 41724 rcv u 41794 179m 41729 snd / 41794 179m dr vrc on char 0 41734 unl 7 41790 179- 41739 trs o 11 41774 1pgm 7 41744 tra i 01 41774 17xm error routine 41749 Sel 2 0500 41754 wr r 41796 179o 41759 tra i 03 41769 17fr 41764 tr 1 41774 177m 41769 hlt j 0418 41774 tra i 02 41589 15qr 41779 rcv u 0306 41784 tr 1 01 00204 02 4 41789 tr 1 41809 180r to next routine 7 2 005 41794 11111 2 001 41795 1 2 005 41800 418 c 2 001 41801 | 7 7 routine #419 7 force 901 check on lip with 7 word 3 of casu 15 redundant. 7 test for false 901 once wr 7 is redundant 7 41809 nop a 45539 553r sw- bypass on chan operation 7 41814 eem 3 14 00000 0+-0 41819 spc , 3700 41824 set b 0008 set up casu 15 41829 lod 8 41994 199m with 41834 set b 0032 redundant 41839 sb % 08 41986 1r8o word 3 41844 sb % 08 41985 1r8n and 41849 spc , 3736 tf 901 41854 lod 8 41986 198o 41859 sb % 11 41986 1rho 41864 sb % 10 41985 1rqn 41869 trs o 11 41874 1qgm 7 41874 lip , 15 00009 0++9 do lip 41879 trs o 11 41909 1r+r and test 901 7 41884 spc , 3700 41889 set b 0000 41894 set b 0032 41899 spc , 0000 41904 tr 1 41939 193r 7 41909 spc , 3700 clear casu 15 41914 set b 0000 and test for 41919 set b 0032 false 901 41924 spc , 0000 41929 trs o 11 41939 1rcr 41934 tr 1 41969 196r 7 41939 tra i 01 41969 19wr error routine 41944 Sel 2 0500 41949 wr r 41995 199n 41954 tra i 03 41964 19fm 41959 tr 1 41969 196r 41964 hlt j 0419 41969 tra i 02 41814 18jm 41974 rcv u 0306 41979 tr 1 01 00204 02 4 41984 tr 1 42009 200r to next routine 7 2 006 41990 24-+-- 3 41994 41879 187r 2 005 41999 419 c 2 001 42000 | 7 7 routine #420 7 test wr vrc char 0 using 7 lip instruction to force 901 7 a. 1 bit 7 b. cba 42 bits 7 c. c a8 21 bits 7 d. b 84 bits 7 42009 eem 3 14 00000 0+-0 42014 spc , 0000 42019 set b 0020 42024 lod 8 42245 224n lod reset field 42029 sb % 08 42241 2k4j 42034 sb % 08 42236 2k3o make 4 redundant 42039 sb % 08 42231 2k3j test character 1 f , * 42044 sb % 08 42226 2k2o 42049 spc , 3700 42054 set b 0032 42059 lod 8 42277 227p reset casu 15 7 42064 spc , 3730 a. 1 bit 42069 lfc , 02 42226 22ko 42074 trs o 11 42079 2-gr tf 901 42079 lip , 15 03700 3g+0 force wr vrc char. 0 42084 trs o 11 42094 2-im 42089 tr 1 42159 215r 7 42094 lfc , 02 42231 22lj b cba42 bits 42099 trs o 11 42104 2j+m tf 901 42104 lip , 15 03700 3g+0 force wr vrc char. 0 42109 trs o 11 42119 2jar 42114 tr 1 42159 215r 7 42119 lfc , 02 42236 22lo c ca821 bits 42124 trs o 11 42129 2jbr tf 901 42129 lip , 15 03700 3g+0 force wr vrc char. 0 42134 trs o 11 42144 2jdm 42139 tr 1 42159 215r 7 42144 lfc , 02 42241 22mj c b84 bits 42149 trs o 11 42154 2jem tf 901 42154 lip , 15 03700 3g+0 force wr vrc char. 0 7 42159 set b 0000 reset 42164 spc , 0000 redundant 42169 unl 7 42245 224n test characters 42174 trs o 11 42209 2k+r 7 42179 tra i 01 42209 22 r error routine 42184 Sel 2 0500 42189 wr r 42278 227q 42194 tra i 03 42204 22+m 42199 tr 1 42209 220r 42204 hlt j 0420 42209 tra i 02 42009 20-r 42214 rcv u 0306 42219 tr 1 01 00204 02 4 42224 tr 1 42289 228r to next routine 7 2 021 42245 -1----f----,----*---- test characters 2 032 42277 3730 casu 15 reset 2 005 42282 420 c 2 001 42283 | 7 7 routine #421 7 test wr vrc char 1 using 7 lip instruction to force 901 7 a. 1 bit 7 b. cba 42 bits 7 c. c a8 21 bits 7 d. b 84 bits 7 42289 eem 3 14 00000 0+-0 42294 spc , 0000 42299 set b 0020 42304 lod 8 42525 252n lod reset field 42309 sb % 08 42521 2n2j 42314 sb % 08 42516 2n1o make 4 redundant 42319 sb % 08 42511 2n1j test character 1 f , * 42324 sb % 08 42506 2n0o 42329 spc , 3700 42334 set b 0032 42339 lod 8 42557 255p reset casu 15 7 42344 spc , 3731 a. 1 bit 42349 lfc , 02 42506 25-o 42354 trs o 11 42359 2ler tf 901 42359 lip , 15 03700 3g+0 force wr vrc char. 1 42364 trs o 11 42374 2lgm 42369 tr 1 42439 243r 7 42374 lfc , 02 42511 25jj b cba42 bits 42379 trs o 11 42384 2lhm tf 901 42384 lip , 15 03700 3g+0 force wr vrc char. 1 42389 trs o 11 42399 2lir 42394 tr 1 42439 243r 7 42399 lfc , 02 42516 25jo c ca821 bits 42404 trs o 11 42409 2m+r tf 901 42409 lip , 15 03700 3g+0 force wr vrc char. 1 42414 trs o 11 42424 2mbm 42419 tr 1 42439 243r 7 42424 lfc , 02 42521 25kj c b84 bits 42429 trs o 11 42434 2mcm tf 901 42434 lip , 15 03700 3g+0 force wr vrc char. 1 7 42439 set b 0000 reset 42444 spc , 0000 redundant 42449 unl 7 42525 252n test characters 42454 trs o 11 42489 2mhr 7 42459 tra i 01 42489 24yr error routine 42464 Sel 2 0500 42469 wr r 42558 255q 42474 tra i 03 42484 24hm 42479 tr 1 42489 248r 42484 hlt j 0421 42489 tra i 02 42289 22qr 42494 rcv u 0306 42499 tr 1 01 00204 02 4 42504 tr 1 42569 256r to next routine 7 2 021 42525 -1----f----,----*---- test characters 2 032 42557 3731 casu 15 reset 2 005 42562 421 c 2 001 42563 | 7 7 routine #422 7 test wr vrc char 2 using 7 lip instruction to force 901 7 a. 1 bit 7 b. cba 42 bits 7 c. c a8 21 bits 7 d. b 84 bits 7 42569 eem 3 14 00000 0+-0 42574 spc , 0000 42579 set b 0020 42584 lod 8 42805 280n lod reset field 42589 sb % 08 42801 2q0j 42594 sb % 08 42796 2p9o make 4 redundant 42599 sb % 08 42791 2p9j test character 1 f , * 42604 sb % 08 42786 2p8o 42609 spc , 3700 42614 set b 0032 42619 lod 8 42837 283p reset casu 15 7 42624 spc , 3732 a. 1 bit 42629 lfc , 02 42786 27qo 42634 trs o 11 42639 2ocr tf 901 42639 lip , 15 03700 3g+0 force wr vrc char. 2 42644 trs o 11 42654 2oem 42649 tr 1 42719 271r 7 42654 lfc , 02 42791 27rj b cba42 bits 42659 trs o 11 42664 2ofm tf 901 42664 lip , 15 03700 3g+0 force wr vrc char. 2 42669 trs o 11 42679 2ogr 42674 tr 1 42719 271r 7 42679 lfc , 02 42796 27ro c ca821 bits 42684 trs o 11 42689 2ohr tf 901 42689 lip , 15 03700 3g+0 force wr vrc char. 2 42694 trs o 11 42704 2p+m 42699 tr 1 42719 271r 7 42704 lfc , 02 42801 28-j c b84 bits 42709 trs o 11 42714 2pam tf 901 42714 lip , 15 03700 3g+0 force wr vrc char. 2 7 42719 set b 0000 reset 42724 spc , 0000 redundant 42729 unl 7 42805 280n test characters 42734 trs o 11 42769 2pfr 7 42739 tra i 01 42769 27wr error routine 42744 Sel 2 0500 42749 wr r 42838 283q 42754 tra i 03 42764 27fm 42759 tr 1 42769 276r 42764 hlt j 0422 42769 tra i 02 42569 25or 42774 rcv u 0306 42779 tr 1 01 00204 02 4 42784 tr 1 42849 284r to next routine 7 2 021 42805 -1----f----,----*---- test characters 2 032 42837 3732 casu 15 reset 2 005 42842 422 c 2 001 42843 | 7 7 routine #423 7 test wr vrc char 3 using 7 lip instruction to force 901 7 a. 1 bit 7 b. cba 42 bits 7 c. c a8 21 bits 7 d. b 84 bits 7 42849 eem 3 14 00000 0+-0 42854 spc , 0000 42859 set b 0020 42864 lod 8 43085 308n lod reset field 42869 sb % 08 43081 3-8j 42874 sb % 08 43076 3-7o make 4 redundant 42879 sb % 08 43071 3-7j test character 1 f , * 42884 sb % 08 43066 3-6o 42889 spc , 3700 42894 set b 0032 42899 lod 8 43117 311p reset casu 15 7 42904 spc , 3733 a. 1 bit 42909 lfc , 02 43066 30oo 42914 trs o 11 42919 2rar tf 901 42919 lip , 15 03700 3g+0 force wr vrc char. 3 42924 trs o 11 42934 2rcm 42929 tr 1 42999 299r 7 42934 lfc , 02 43071 30pj b cba42 bits 42939 trs o 11 42944 2rdm tf 901 42944 lip , 15 03700 3g+0 force wr vrc char. 3 42949 trs o 11 42959 2rer 42954 tr 1 42999 299r 7 42959 lfc , 02 43076 30po c ca821 bits 42964 trs o 11 42969 2rfr tf 901 42969 lip , 15 03700 3g+0 force wr vrc char. 3 42974 trs o 11 42984 2rhm 42979 tr 1 42999 299r 7 42984 lfc , 02 43081 30qj c b84 bits 42989 trs o 11 42994 2rim tf 901 42994 lip , 15 03700 3g+0 force wr vrc char. 3 7 42999 set b 0000 reset 43004 spc , 0000 redundant 43009 unl 7 43085 308n test characters 43014 trs o 11 43049 3-dr 7 43019 tra i 01 43049 30ur error routine 43024 Sel 2 0500 43029 wr r 43118 311q 43034 tra i 03 43044 30dm 43039 tr 1 43049 304r 43044 hlt j 0423 43049 tra i 02 42849 28mr 43054 rcv u 0306 43059 tr 1 01 00204 02 4 43064 tr 1 43129 312r to next routine 7 2 021 43085 -1----f----,----*---- test characters 2 032 43117 3733 casu 15 reset 2 005 43122 423 c 2 001 43123 | 7 7 routine #424 7 test wr vrc char 4 using 7 lip instruction to force 901 7 a. 1 bit 7 b. cba 42 bits 7 c. c a8 21 bits 7 d. b 84 bits 7 43129 eem 3 14 00000 0+-0 43134 spc , 0000 43139 set b 0020 43144 lod 8 43365 336n lod reset field 43149 sb % 08 43361 3l6j 43154 sb % 08 43356 3l5o make 4 redundant 43159 sb % 08 43351 3l5j test character 1 f , * 43164 sb % 08 43346 3l4o 43169 spc , 3700 43174 set b 0032 43179 lod 8 43397 339p reset casu 15 7 43184 spc , 3734 a. 1 bit 43189 lfc , 02 43346 33mo 43194 trs o 11 43199 3jir tf 901 43199 lip , 15 03700 3g+0 force wr vrc char. 4 43204 trs o 11 43214 3kam 43209 tr 1 43279 327r 7 43214 lfc , 02 43351 33nj b cba42 bits 43219 trs o 11 43224 3kbm tf 901 43224 lip , 15 03700 3g+0 force wr vrc char. 4 43229 trs o 11 43239 3kcr 43234 tr 1 43279 327r 7 43239 lfc , 02 43356 33no c ca821 bits 43244 trs o 11 43249 3kdr tf 901 43249 lip , 15 03700 3g+0 force wr vrc char. 4 43254 trs o 11 43264 3kfm 43259 tr 1 43279 327r 7 43264 lfc , 02 43361 33oj c b84 bits 43269 trs o 11 43274 3kgm tf 901 43274 lip , 15 03700 3g+0 force wr vrc char. 4 7 43279 set b 0000 reset 43284 spc , 0000 redundant 43289 unl 7 43365 336n test characters 43294 trs o 11 43329 3lbr 7 43299 tra i 01 43329 33sr error routine 43304 Sel 2 0500 43309 wr r 43398 339q 43314 tra i 03 43324 33bm 43319 tr 1 43329 332r 43324 hlt j 0424 43329 tra i 02 43129 31kr 43334 rcv u 0306 43339 tr 1 01 00204 02 4 43344 tr 1 43409 340r to next routine 7 2 021 43365 -1----f----,----*---- test characters 2 032 43397 3734 casu 15 reset 2 005 43402 424 c 2 001 43403 | 7 7 routine #425 7 test wr vrc char 5 using 7 lip instruction to force 901 7 a. 1 bit 7 b. cba 42 bits 7 c. c a8 21 bits 7 d. b 84 bits 7 43409 eem 3 14 00000 0+-0 43414 spc , 0000 43419 set b 0020 43424 lod 8 43645 364n lod reset field 43429 sb % 08 43641 3o4j 43434 sb % 08 43636 3o3o make 4 redundant 43439 sb % 08 43631 3o3j test character 1 f , * 43444 sb % 08 43626 3o2o 43449 spc , 3700 43454 set b 0032 43459 lod 8 43677 367p reset casu 15 7 43464 spc , 3735 a. 1 bit 43469 lfc , 02 43626 36ko 43474 trs o 11 43479 3mgr tf 901 43479 lip , 15 03700 3g+0 force wr vrc char. 5 43484 trs o 11 43494 3mim 43489 tr 1 43559 355r 7 43494 lfc , 02 43631 36lj b cba42 bits 43499 trs o 11 43504 3n+m tf 901 43504 lip , 15 03700 3g+0 force wr vrc char. 5 43509 trs o 11 43519 3nar 43514 tr 1 43559 355r 7 43519 lfc , 02 43636 36lo c. ca821 bits 43524 trs o 11 43529 3nbr tf 901 43529 lip , 15 03700 3g+0 force wr vrc char. 5 43534 trs o 11 43544 3ndm 43539 tr 1 43559 355r 7 43544 lfc , 02 43641 36mj d. b84 bits 43549 trs o 11 43554 3nem tf 901 43554 lip , 15 03700 3g+0 force wr vrc char. 5 7 43559 set b 0000 reset 43564 spc , 0000 redundant 43569 unl 7 43645 364n test characters 43574 trs o 11 43609 3o+r 7 43579 tra i 01 43609 36 r error routine 43584 Sel 2 0500 43589 wr r 43678 367q 43594 tra i 03 43604 36+m 43599 tr 1 43609 360r 43604 hlt j 0425 43609 tra i 02 43409 34-r 43614 rcv u 0306 43619 tr 1 01 00204 02 4 43624 tr 1 43689 368r to next routine 7 2 021 43645 -1----f----,----*---- test characters 2 032 43677 3735 casu 15 reset 2 005 43682 425 c 2 001 43683 | 7 7 routine #426 7 test wr vrc char 6 using 7 lip instruction to force 901 7 a. 1 bit 7 b. cba 42 bits 7 c. c a8 21 bits 7 d. b 84 bits 7 43689 eem 3 14 00000 0+-0 43694 spc , 0000 43699 set b 0020 43704 lod 8 43925 392n lod reset field 43709 sb % 08 43921 3r2j 43714 sb % 08 43916 3r1o make 4 redundant 43719 sb % 08 43911 3r1j test character 1 f , * 43724 sb % 08 43906 3r0o 43729 spc , 3700 43734 set b 0032 43739 lod 8 43957 395p reset casu 15 7 43744 spc , 3736 a. 1 bit 43749 lfc , 02 43906 39-o 43754 trs o 11 43759 3per tf 901 43759 lip , 15 03700 3g+0 force wr vrc char. 6 43764 trs o 11 43774 3pgm 43769 tr 1 43839 383r 7 43774 lfc , 02 43911 39jj b cba42 bits 43779 trs o 11 43784 3phm tf 901 43784 lip , 15 03700 3g+0 force wr vrc char. 6 43789 trs o 11 43799 3pir 43794 tr 1 43839 383r 7 43799 lfc , 02 43916 39jo c. ca821 bits 43804 trs o 11 43809 3q+r tf 901 43809 lip , 15 03700 3g+0 force wr vrc char. 6 43814 trs o 11 43824 3qbm 43819 tr 1 43839 383r 7 43824 lfc , 02 43921 39kj d. b84 bits 43829 trs o 11 43834 3qcm tf 901 43834 lip , 15 03700 3g+0 force wr vrc char. 6 7 43839 set b 0000 reset 43844 spc , 0000 redundant 43849 unl 7 43925 392n test characters 43854 trs o 11 43889 3qhr 7 43859 tra i 01 43889 38yr error routine 43864 Sel 2 0500 43869 wr r 43958 395q 43874 tra i 03 43884 38hm 43879 tr 1 43889 388r 43884 hlt j 0426 43889 tra i 02 43689 36qr 43894 rcv u 0306 43899 tr 1 01 00204 02 4 43904 tr 1 43969 396r to next routine 7 2 021 43925 -1----f----,----*---- test characters 2 032 43957 3736 casu 15 reset 2 005 43962 426 c 2 001 43963 | 7 7 routine #427 7 test wr vrc char 7 using 7 lip instruction to force 901 7 a. 1 bit 7 b. cba 42 bits 7 c. c a8 21 bits 7 d. b 84 bits 7 43969 eem 3 14 00000 0+-0 43974 spc , 0000 43979 set b 0020 43984 lod 8 44205 420n lod reset field 43989 sb % 08 44201 4k0j 43994 sb % 08 44196 4j9o make 4 redundant 43999 sb % 08 44191 4j9j test character 1 f , * 44004 sb % 08 44186 4j8o 44009 spc , 3700 44014 set b 0032 44019 lod 8 44237 423p reset casu 15 7 44024 spc , 3737 a. 1 bit 44029 lfc , 02 44186 41qo 44034 trs o 11 44039 4-cr tf 901 44039 lip , 15 03700 3g+0 force wr vrc char. 7 44044 trs o 11 44054 4-em 44049 tr 1 44119 411r 7 44054 lfc , 02 44191 41rj b cba42 bits 44059 trs o 11 44064 4-fm tf 901 44064 lip , 15 03700 3g+0 force wr vrc char. 7 44069 trs o 11 44079 4-gr 44074 tr 1 44119 411r 7 44079 lfc , 02 44196 41ro c. ca821 bits 44084 trs o 11 44089 4-hr tf 901 44089 lip , 15 03700 3g+0 force wr vrc char. 7 44094 trs o 11 44104 4j+m 44099 tr 1 44119 411r 7 44104 lfc , 02 44201 42-j d. b84 bits 44109 trs o 11 44114 4jam tf 901 44114 lip , 15 03700 3g+0 force wr vrc char. 7 7 44119 set b 0000 reset 44124 spc , 0000 redundant 44129 unl 7 44205 420n test characters 44134 trs o 11 44169 4jfr 7 44139 tra i 01 44169 41wr error routine 44144 Sel 2 0500 44149 wr r 44238 423q 44154 tra i 03 44164 41fm 44159 tr 1 44169 416r 44164 hlt j 0427 44169 tra i 02 43969 39or 44174 rcv u 0306 44179 tr 1 01 00204 02 4 44184 tr 1 44249 424r to next routine 7 2 021 44205 -1----f----,----*---- test characters 2 032 44237 3737 casu 15 reset 2 005 44242 427 c 2 001 44243 | 7 7 routine #428 7 a. do lip to force 900, 901 7 checks and test both on 7 b. do lip to reset 900, 901 7 checks and test both off 7 44249 eem 3 14 00000 0+-0 set up casu 15 44254 spc , 3700 with 900 and 901 44259 set b 0008 status bits 44264 lod 8 44409 440r 44269 set b 0032 7 44274 lip , 15 00009 0++9 force 900 and 901 on 44279 trs o 10 44289 4kqr and test 44284 tr 1 44354 435m 44289 trs o 11 44299 4kir 44294 tr 1 44354 435m 7 44299 spc , 3700 set up casu 15 without 44304 set b 0008 900 and 901 status bits 44309 lod 8 44419 441r 44314 set b 0032 44319 sb % 08 44321 4l2j 44324 sb % 08 44321 4l2j turn 900 and 901 on 7 44329 lip , 15 00009 0++9 reset 900 and 901 off 44334 trs o 10 44354 4lnm and test 44339 trs o 11 44354 4lem 44344 tr 1 44384 438m 44349 trs o 11 44354 4lem 7 44354 tra i 01 44384 43ym error routine 44359 Sel 2 0500 44364 wr r 44420 442- 44369 tra i 03 44379 43gr 44374 tr 1 44384 438m 44379 hlt j 0428 44384 tra i 02 44249 42mr 44389 rcv u 0306 44394 tr 1 01 00204 02 4 44399 tr 1 44434 443m to next routine 7 2 006 44405 00-+l- 3 44409 44279 427r 2 006 44415 00-+-- 3 44419 44334 433m 2 005 44424 428 c 2 001 44425 | 7 7 routine #429 7 do tip with 900 and 901 on. 7 test stoing of status bits 7 44434 eem 3 14 00000 0+-0 clear casu 15 44439 spc , 3700 44444 set b 0000 44449 set b 0032 44454 sb % 08 44458 4m5q 44459 sb % 08 44458 4m5q tn 900 and 901 checks 7 44464 tip , 14 44469 4dor do tip and 44469 trs o 11 44474 4mgm test status 44474 spc , 3705 bits stored 44479 set b 0001 44484 cmp 4 44610 461- 44489 tre l 44524 452m 7 44494 spc , 3700 error reset 44499 set b 0008 44504 lod 8 44609 460r 44509 set b 0028 44514 lip , 15 00009 0++9 44519 tr 1 44554 455m 7 44524 spc , 3700 good reset 44529 set b 0008 44534 lod 8 44619 461r 44539 set b 0028 44544 lip , 15 00009 0++9 44549 tr 1 44584 458m 7 44554 tra i 01 44584 45ym error routine 44559 Sel 2 0500 44564 wr r 44620 462- 44569 tra i 03 44579 45gr 44574 tr 1 44584 458m 44579 hlt j 0429 44584 tra i 02 44434 44lm 44589 rcv u 0306 44594 tr 1 01 00204 02 4 44599 tr 1 44634 463m to next routine 7 2 006 44605 00-+-- status and ic from lip-error 3 44609 44519 451r 2 006 44615 l--+-- status and ic from lip-good 3 44619 44549 454r 2 005 44624 429 c 2 001 44625 | 7 7 routine #430 7 force 902 check and test 7 sel 0902-trs. also test for 7 false transfers. 7 44634 eem 3 14 00000 0+-0 set up casu 15 with 44639 spc , 3700 902 status bit 44644 set b 0008 and do lip 44649 lod 8 44764 476m 44654 set b 0032 44659 lip , 15 00009 0++9 7 44664 nop a 12 44699 4f9r test for 44669 sel 2 0902 false 44674 trs o 13 44699 4fzr transfers 7 44679 trs o 44689 468r do trs 44684 tr 1 44699 469r twice to 44689 trs o 44699 469r check 902 turned off 44694 tr 1 44734 473m 7 44699 trs o 12 44704 4g0m error routine 44704 tra i 01 44734 47tm 44709 Sel 2 0500 44714 wr r 44750 475- 44719 tra i 03 44729 47br 44724 tr 1 44734 473m 44729 hlt j 0430 44734 tra i 02 44634 46lm 44739 rcv u 0306 44744 tr 1 01 00204 02 4 44749 tr 1 44769 476r to next routine 7 2 005 44754 430 c 2 001 44755 | 2 005 44760 0-+m- status and ic from lip 3 44764 44664 466m 7 7 routine #431 7 force 902 check and test 7 trs 12. also test for false 7 transfer. 7 44769 eem 3 14 00000 0+-0 set up casu 15 with 44774 spc , 3700 902 status bit 44779 set b 0008 and do lip 44784 lod 8 44899 489r 44789 set b 0032 44794 lip , 15 00009 0++9 7 44799 sel 2 0000 test false 44804 trs o 44829 482r transfers 7 44809 trs o 12 44819 4h1r do trs 12 44814 tr 1 44829 482r twice to check 44819 trs o 12 44829 4h2r that 902 turned off 44824 tr 1 44869 486r 7 44829 sel 2 0902 error reset 902 44834 trs o 44839 483r transfers 7 44839 tra i 01 44869 48wr error routine 44844 Sel 2 0500 44849 wr r 44885 488n 44854 tra i 03 44864 48fm 44859 tr 1 44869 486r 44864 hlt j 0431 44869 tra i 02 44769 47or 44874 rcv u 0306 44879 tr 1 01 00204 02 4 44884 tr 1 44904 490m to next routine 7 2 005 44889 431 c 2 001 44890 | 2 005 44895 0-+m- status and ic from lip 3 44899 44799 479r 7 7 routine #432 7 force 903 check and test 7 sel 0903-trs. also test 7 for false transfers. 7 44904 eem 3 14 00000 0+-0 set up casu 15 with 44909 spc , 3700 903 status bit 44914 set b 0008 and do lip 44919 lod 8 45034 503m 44924 set b 0032 44929 lip , 15 00009 0++9 7 44934 nop a 13 44969 4iwr test for 44939 sel 2 0903 false 44944 trs o 12 44969 4i6r transfers 7 44949 trs o 44959 495r to trs twice 44954 tr 1 44969 496r to check that 44959 trs o 44969 496r 903 turned off 44964 tr 1 45004 500m 7 44969 trs o 13 44974 4ixm error routine 44974 tra i 01 45004 50 m 44979 Sel 2 0500 44984 wr r 45020 502- 44989 tra i 03 44999 49ir 44994 tr 1 45004 500m 44999 hlt j 0432 45004 tra i 02 44904 49-m 45009 rcv u 0306 45014 tr 1 01 00204 02 4 45019 tr 1 45039 503r to next routine 7 2 005 45024 432 c 2 001 45025 | 2 005 45030 0-++- status and ic from lip 3 45034 44934 493m 7 7 routine #433 7 force 903 check and test 7 trs 13. also test for false 7 transfer. 7 45039 eem 3 14 00000 0+-0 set up casu 15 with 45044 spc , 3700 903 status bit 45049 set b 0008 and do lip 45054 lod 8 45169 516r 45059 set b 0032 45064 lip , 15 00009 0++9 7 45069 sel 2 0000 test false 45074 trs o 45099 509r transfers 7 45079 trs o 13 45089 5+yr do trs 13 twice 45084 tr 1 45099 509r to check that 45089 trs o 13 45099 5+zr 903 turned off 45094 tr 1 45139 513r 7 45099 sel 2 0903 error reset 903 45104 trs o 45109 510r transfers 7 45109 tra i 01 45139 51tr error routine 45114 Sel 2 0500 45119 wr r 45155 515n 45124 tra i 03 45134 51cm 45129 tr 1 45139 513r 45134 hlt j 0433 45139 tra i 02 45039 50lr 45144 rcv u 0306 45149 tr 1 01 00204 02 4 45154 tr 1 45174 517m to next routine 7 2 005 45159 433 c 2 001 45160 | 2 005 45165 0-++- status and ic from lip 3 45169 45069 506r 7 7 routine #434 7 do lip to reset 902 and 903 7 triggers off. 7 45174 eem 3 14 00000 0+-0 set up casu 15 with 45179 spc , 3700 status bits to turn on 45184 set b 0008 902 and 903 triggers 45189 lod 8 45304 530m 45194 set b 0032 45199 lip , 15 00009 0++9 7 45204 spc , 3700 clear 902 and 903 45209 lfc , 02 45314 53jm status bits and 45214 spc , 3704 lip 45219 lfc , 02 45309 53-r 45224 lip , 15 00009 0++9 7 45229 trs o 12 45244 5b4m test 902 45234 trs o 13 45244 5bum and 903 45239 tr 1 45279 527r 7 45244 trs o 13 45249 5bur error routine 45249 tra i 01 45279 52xr 45254 Sel 2 0500 45259 wr r 45315 531n 45264 tra i 03 45274 52gm 45269 tr 1 45279 527r 45274 hlt j 0434 45279 tra i 02 45174 51pm 45284 rcv u 0306 45289 tr 1 01 00204 02 4 45294 tr 1 45329 532r to next routine 7 7 constants 2 006 45300 00-+D- status to tn 902 and 903 3 45304 45204 520m 2 006 45310 0-+--0 status to reset 902 and 903 3 45314 45229 522r 2 005 45319 434 c 2 001 45320 | 7 7 routine #435 7 do tip to pick up 902 and 903 7 status bits test for correct 7 status and also test for false 7 bit pick up in storage. 7 45329 eem 3 14 00000 0+-0 set up casu 15 with 45334 spc , 3700 status bits to turn on 45339 set b 0008 902 and 903 triggers 45344 lod 8 45519 551r 45349 set b 0032 45354 lip , 15 00009 0++9 7 45359 spc , 0005 45364 set b 0001 45369 lod 8 45520 552- do lod 7 45374 spc , 3704 45379 lfc , 02 45524 55km clear status in casu 15 45384 spc , 0000 45389 tip , 14 45394 5crm 45394 trs o 12 45399 5c9r turn off 45399 trs o 13 45404 5d m 902 and 903 45404 spc , 3704 and test 45409 set b 0002 status 45414 cmp 4 45527 552p bits 45419 tre l 45429 542r 45424 tr 1 45459 545r 7 45429 spc , 0005 test result of 45434 cmp 4 45525 552n lod 45439 tre l 45449 544r 45444 tr 1 45459 545r 7 45449 lip , 15 03700 3g+0 lip-good 45454 tr 1 45494 549m 45459 lip , 15 03700 3g+0 7 45464 tra i 01 45494 54zm error routine 45469 Sel 2 0500 45474 wr r 45528 552q 45479 tra i 03 45489 54hr 45484 tr 1 45494 549m 45489 hlt j 0435 45494 tra i 02 45329 53kr 45499 rcv u 0306 45504 tr 1 01 00204 02 4 45509 tr 1 45539 553r to next routine 7 2 006 45515 00-+D- status to tn 902 and 903 3 45519 45359 535r 2 005 45524 1-+-- status to reset 902 and 903 2 003 45527 1d- 2 005 45532 435 c 2 001 45533 | 7 7 routine #436 7 do add and force 904 check 7 test for false transfer, and 7 test sel 0904-trs 00. 7 45539 rad h 45579 557r 45544 add g 45579 557r force 904 45549 nop a 14 45584 5eqm 7 45554 sel 2 0904 do trs twice 45559 trs o 45569 556r to check that 45564 tr 1 45584 558m 904 turned off 45569 trs o 45569 556r to check that 45574 tr 1 45614 561m 45579 nop a 0iii 7 45584 tra i 01 45614 56/m error routine 45589 Sel 2 0500 45594 wr r 45630 563- 45599 tra i 03 45609 56+r 45604 tr 1 45614 561m 45609 hlt j 0436 45614 tra i 02 45539 55lr 45619 rcv u 0306 45624 tr 1 01 00204 02 4 45629 tr 1 45644 564m to next routine 7 2 005 45634 436 c 2 001 45635 | 7 7 routine #437 7 do sub and force 904 check 7 test for false transfer, and 7 and test trs 14. 7 45644 rsu q 45746 574o 45649 sub p 45746 574o force 904 7 45654 sel 2 0904 test for 45659 trs o 15 45694 5fim false 45664 sel 2 0000 transfer 45669 trs o 45694 569m to check that 7 45674 trs o 14 45684 5fqm test trs 14 45679 tr 1 45694 569m 45684 trs o 14 45694 5frm 45689 tr 1 45729 572r 7 45694 trs o 14 45699 5frr error routine 45699 tra i 01 45729 57sr 45704 Sel 2 0500 45709 wr r 45747 574p 45714 tra i 03 45724 57bm 45719 tr 1 45729 572r 45724 hlt j 0437 45729 tra i 02 45644 56mm 45734 rcv u 0306 45739 tr 1 01 00204 02 4 45744 tr 1 45759 575r to next routine 7 2 002 45746 II 2 005 45751 437 c 2 001 45752 | 7 7 routine #438 7 force 904 on round into 7 storage mark and test 904. 7 also check for bit pick up 7 in storage char. 6. 7 45759 eem 3 14 00000 0+-0 45764 spc , 0000 45769 set b 0000 45774 rnd e 0001 force 904 45779 spc , 0006 45784 set b 0001 45789 lod 8 45867 586p lod char. 6 with 904 on 7 45794 trs o 14 45804 5h-m test 904 45799 tr 1 45814 581m 45804 cmp 4 45866 586o test storage char 6 45809 tre l 45844 584m 7 45814 tra i 01 45844 58um error routine 45819 Sel 2 0500 45824 wr r 45860 586- 45829 tra i 03 45839 58cr 45834 tr 1 45844 584m 45839 hlt j 0438 45844 tra i 02 45759 57nr 45849 rcv u 0306 45854 tr 1 01 00204 02 4 45859 tr 1 45874 587m to next routine 7 2 005 45864 438 c 2 001 45865 | 2 002 45867 ++ 7 7 routine #439 7 force 904 on round into 7 carry into storage mark. 7 test 904 and storage 7 result equal 10. 7 45874 eem 3 14 00000 0+-0 45879 spc , 0000 reset spc 45884 set b 0002 45889 lod 8 45972 597k 99 45894 rnd e 0001 force 904 7 45899 trs o 14 45909 5i-r test 904 45904 tr 1 45919 591r 45909 cmp 4 45974 597m test storage equal 10 45914 tre l 45949 594r 7 45919 tra i 01 45949 59ur error routine 45924 Sel 2 0500 45929 wr r 45965 596n 45934 tra i 03 45944 59dm 45939 tr 1 45949 594r 45944 hlt j 0439 45949 tra i 02 45874 58pm 45954 rcv u 0306 45959 tr 1 01 00204 02 4 45964 tr 1 45979 597r to next routine 7 2 005 45969 439 c 2 001 45970 | 2 002 45972 99 2 002 45974 10 7 7 routine #440 7 force 904 check on divide 7 a. divide minus 57 by plus 2 7 b. divide plus 10 by minus 1 7 test 904, zero and signs 7 45979 eem 3 14 00000 0+-0 45984 spc , 0000 reset spc 45989 rad h 46144 614m 45994 div w 46147 614p aux 3 is on in div tc 5, 45999 trs o 14 46009 6+-r tn aux 2 and end op in tc 2. 46004 tr 1 46089 608r 46009 trz n 46019 601r test zero 46014 tr 1 46089 608r 46019 trp m 46089 608r test minus 7 46024 spc , 0000 46029 rad h 46150 615- 46034 div w 46153 615l aux 3 is off in div tc 5, 46039 trs o 14 46049 6+mr tn aux 2 and end op in tc 2. 46044 tr 1 46089 608r 46049 trz n 46059 605r test zero 46054 tr 1 46089 608r 46059 trp m 46069 606r test minus 46064 tr 1 46089 608r 7 46069 cmp 4 46140 614- check single 0 quotient 46074 tre l 46089 608r for not a storage mark 46079 cmp 4 46141 614j and equal zero. 46084 tre l 46119 611r 7 46089 tra i 01 46119 61/r error routine 46094 Sel 2 0500 46099 wr r 46135 613n 46104 tra i 03 46114 61am 46109 tr 1 46119 611r 46114 hlt j 0440 46119 tra i 02 45979 59pr 46124 rcv u 0306 46129 tr 1 01 00204 02 4 46134 tr 1 46159 615r to next routine 7 2 005 46139 440 c 2 001 46140 | 2 001 46141 0 2 006 46147 x5p xb 2 006 46153 x1+ xj 7 7 routine #441 7 do rad and force 905 check 7 test sel 0905 trs 00,and 7 test for false transfers 7 46159 rad h 46214 621m force 905 check 46164 sel 2 0905 and test for 46169 nop a 15 46219 6bar false transfer 46174 trs o 14 46219 6bjr 46179 sel 2 0000 46184 trs o 46219 621r 7 46189 sel 2 0905 test trs twice 46194 trs o 46204 620m to check that 46199 tr 1 46219 621r 905 turned off 46204 trs o 46219 621r 46209 tr 1 46254 625m 46214 nop a 0000 7 46219 trs o 15 46224 6bbm error routine 46224 tra i 01 46254 62vm 46229 Sel 2 0500 46234 wr r 46270 627- 46239 tra i 03 46249 62dr 46244 tr 1 46254 625m 46249 hlt j 0437 46254 tra i 02 46159 61nr 46259 rcv u 0306 46264 tr 1 01 00204 02 4 46269 tr 1 46284 628m to next routine 7 2 005 46274 441 c 2 001 46275 | 7 7 routine #442 7 force 905 on round into 7 trs 15. also test for bit 7 pickup in storage char.6 7 46284 eem 3 14 00000 0+-0 46289 rad h 46382 638k force 905 46294 spc , 0006 46299 set b 0001 46304 lod 8 46384 638m do lod with 905 on 7 46309 trs o 15 46319 6car 46314 tr 1 46329 632r 46319 cmp 4 46385 638n test storage char 6. 46324 tre l 46359 635r 7 46329 tra i 01 46359 63vr error routine 46334 Sel 2 0500 46339 wr r 46375 637n 46344 tra i 03 46354 63em 46349 tr 1 46359 635r 46354 hlt j 0442 46359 tra i 02 46284 62qm 46364 rcv u 0306 46369 tr 1 01 00204 02 4 46374 tr 1 46394 639m to next routine 7 2 005 46379 442 c 2 001 46380 | 2 005 46385 x5 ++ 7 7 routine #443 7 force and test 905 check 7 from unsigned mpy and div. 7 46394 rad h 46483 648l 46399 mpy v 46485 648n force 905 on mpy 46404 trs o 15 46414 6dam and test 46409 tr 1 46429 642r 7 46414 rad h 46483 648l 46419 div w 46485 648n force 905 on div 46424 trs o 15 46459 6der and test 7 46429 tra i 01 46459 64vr error routine 46434 Sel 2 0500 46439 wr r 46475 647n 46444 tra i 03 46454 64em 46449 tr 1 46459 645r 46454 hlt j 0443 46459 tra i 02 46284 62qm 46464 rcv u 0306 46469 tr 1 01 00204 02 4 46474 tr 1 46494 649m to next routine 7 2 005 46479 443 c 2 001 46480 | 2 005 46485 x4i 7 7 7 routine #444 7 turn on the any trigger and 7 test tra. also test for 7 false transfers. 7 46494 sb % 08 46499 6m9r 46499 sb % 08 46499 6m9r force 900, 901, and any 46504 trs o 10 46509 6n-r tf900 46509 trs o 11 46514 6nam tf901 7 46514 nop a 46544 654m test for 46519 tra i 08 46544 6n4m false transfers 7 46524 tra i 46534 653m do tra twice 46529 tr 1 46544 654m to check that 46534 tra i 46544 654m any turns off 46539 tr 1 46574 657m 7 46544 tra i 01 46574 65xm error routine 46549 Sel 2 0500 46554 wr r 46590 659- 46559 tra i 03 46569 65fr 46564 tr 1 46574 657m 46569 hlt j 0444 46574 tra i 02 46494 64rm 46579 rcv u 0306 46584 tr 1 01 00204 02 4 46589 tr 1 46604 660m to next routine 7 2 005 46594 444 c 2 001 46595 | 7 7 routine #445 7 force any trigger on from 7 900, 901, 904, and 905 7 checks and test individually. 7 46604 lem 3 15 00000 0++0 46609 spc , 0000 900 chk 46614 trs o 10 46619 6ojr 46619 tra i 46629 662r test any 46624 tr 1 46694 669m 7 46629 sb % 08 46748 6p4q 46634 sb % 09 46748 6puq 901 chk 46639 trs o 11 46644 6odm 46644 tra i 46654 665m test any 46649 tr 1 46694 669m 7 46654 rad h 46747 674p 46659 rnd e 0001 904 chk 46664 trs o 14 46669 6for 46669 tra i 46679 667r test any 46674 tr 1 46694 669m 7 46679 rad h 46748 674q 46684 trs o 15 46689 6fhr 46689 tr 1 46724 672m test any 7 46694 tra i 01 46724 67sm error routine 46699 Sel 2 0500 46704 wr r 46740 674- 46709 tra i 03 46719 67ar 46714 tr 1 46724 672m 46719 hlt j 0445 46724 tra i 02 46604 66-m 46729 rcv u 0306 46734 tr 1 01 00204 02 4 46739 tr 1 46754 675m to next routine 7 2 005 46744 445 c 2 001 46745 | 2 003 46748 xi9 7 7 routine #446 7 do tip and test storing of 7 status bits for 904,905, 7 and the any triggeres. 7 46754 nop a 47429 742r sw- bypass on chan operation 7 46759 eem 3 14 00000 0+-0 46764 spc , 3700 46769 set b 0000 clear 46774 set b 0032 casu 15 46779 spc , 0000 7 46784 rad h 46907 690p 46789 add g 46908 690q tn 904, 905, any 46794 tip , 14 46799 6grr 7 46799 trs o 14 46804 6h-m turn off checks 46804 trs o 15 46809 6h+r and test status 46809 tra i 46814 681m 46814 spc , 3705 46819 set b 0001 46824 cmp 4 46910 691- 46829 tr 1 46839 683r 46834 lip , 15 03700 3g+0 lip-good 46839 tr 1 46884 688m 7 46849 lip , 15 03700 3g+0 46854 tra i 01 46884 68ym error routine 46859 Sel 2 0500 46864 wr r 46900 690- 46869 tra i 03 46879 68gr 46874 tr 1 46884 688m 46879 hlt j 0446 46884 tra i 02 46759 67nr 46889 rcv u 0306 46894 tr 1 01 00204 02 4 46899 tr 1 46919 691r to next routine 7 2 005 46904 446 c 2 001 46905 | 2 005 46910 xi9 g 7 7 routine #447 7 do lip and test setting 7 of 904, 905 and any 7 triggers from status bits 7 46919 eem 3 14 00000 0+-0 46924 spc , 3700 set up casu 15 with 46929 set b 0008 status bits for 904, 46934 lod 8 47032 703k 905 and any. 46939 set b 0032 46944 lip , 15 00009 0++9 7 46949 trs o 14 46964 6iom test 904 46954 trs o 15 46959 6ier 46959 tr 1 46979 697r 46964 trs o 15 46974 6igm test 905 46969 tr 1 46979 697r 46974 tra i 47009 700r test any 7 46979 tra i 01 47009 70 r error routine 46984 Sel 2 0500 46989 wr r 47033 703l 46994 tra i 03 47004 70+m 46999 tr 1 47009 700r 47004 hlt j 0447 47009 tra i 02 46919 69jr 47014 rcv u 0306 47019 tr 1 01 00204 02 4 47024 tr 1 47044 704m to next routine 7 2 004 47028 -g-- 3 47032 46949 694r 2 005 47037 447 c 2 001 47038 | 7 7 routine #448 7 do lip and test reset of 7 of 904, 905 and any triggers. 7 47044 eem 3 14 00000 0+-0 47049 spc , 3700 set up casu 15 with 47054 set b 0008 without 904, 47059 lod 8 47157 715p 905 and any status bits 47064 set b 0032 7 47069 rad h 01 47159 71vr 47074 add g 01 47160 71w- tn 904, 905, any 47079 lip , 15 00009 0++9 7 47084 trs o 14 47104 7a-m test 904, 47089 trs o 15 47104 7a+m 905, 47094 tra i 47104 710m and any off 47099 tr 1 47134 713m test 905 7 47104 tra i 01 47134 71tm error routine 47109 Sel 2 0500 47114 wr r 47161 716j 47119 tra i 03 47129 71br 47124 tr 1 47134 713m 47129 hlt j 0448 47134 tra i 02 47044 70mm 47139 rcv u 0306 47144 tr 1 01 00204 02 4 47149 tr 1 47174 717m to next routine 7 2 004 47153 -+-- 3 47157 47084 708m 2 003 47160 xi9 2 005 47165 448 c 2 001 47166 | 7 7 routine #449 7 test bl ad trigger on tip. 7 do tip with sbr char 0 red. 7 and test 901. 7 47174 eem 3 14 00000 0+-0 47179 spc , 3700 47184 sb % 08 47291 7k9j 47189 set b 0001 47194 lod 8 47291 729j red. to char 0 wd 0 casu 15 47199 spc , 0000 47204 sb % 09 47291 7kzj 47209 trs o 11 47214 7kam 7 47214 tip , 14 47219 7bjr 47219 trs o 11 47234 7kcm test 901 47224 lip , 15 03700 3g+0 47229 tr 1 47269 726r 7 47234 lip , 15 03700 3g+0 47239 tra i 01 47269 72wr error routine 47244 Sel 2 0500 47249 wr r 47285 728n 47254 tra i 03 47264 72fm 47259 tr 1 47269 726r 47264 hlt j 0449 47269 tra i 02 47174 71pm 47274 rcv u 0306 47279 tr 1 01 00204 02 4 47284 tr 1 47299 729r to next routine 7 2 005 47289 449 c 2 001 47290 | 2 001 47291 7 7 7 routine #450 7 test bl ad trigger and for 7 false wr check on lip. 7 set sbr char. 0 and wr char. 7 redundant, do lip 3700 7 and test for no 901 check. 7 47299 eem 3 14 00000 0+-0 47304 spc , 0000 47309 tip , 14 47314 7cjm 47314 set b 0001 47319 sb % 08 47421 7m2j 47324 lod 8 47421 742j red. to storage and sbr 47329 lod 8 47421 742j red. to wr 47334 sb % 09 47421 7msj 47339 trs o 11 47344 7ldm 7 47344 lip , 15 03700 3g+0 do lip 47349 trs o 11 47364 7lfm test 901 47354 set b 0000 47359 tr 1 47399 739r 7 47364 set b 0000 47369 tra i 01 47399 73zr error routine 47374 Sel 2 0500 47379 wr r 47415 741n 47384 tra i 03 47394 73im 47389 tr 1 47399 739r 47394 hlt j 0450 47399 tra i 02 47299 72rr 47404 rcv u 0306 47409 tr 1 01 00204 02 4 47414 tr 1 47429 742r to next routine 7 2 005 47419 450 s 2 001 47420 | 2 001 47421 7 7 7 routine #451 7 test tzb for check 7 suppression. no 901 on 7 forced 900 chk and sbr red. 7 47429 sb % 08 47454 7m5m tzb inst. redundant 47434 set b 01 00001 00 1 47439 lod 8 01 47454 74vm sbr char. 0 red 47444 trs o 11 47449 7mdr 47449 rcv u 0004 47454 tzb . 08 47459 7m5r 47459 trs o 10 47464 7mom 47464 trs o 11 47484 7mhm test 901 47469 lod 8 01 47549 75ur 47474 unl 7 01 47454 74vm 47479 tr 1 47524 752m 7 47484 lod 8 01 47549 75ur error reset 47489 unl 7 01 47454 74vm 7 47494 tra i 01 47524 75sm error routine 47499 Sel 2 0500 47504 wr r 47540 754- 47509 tra i 03 47519 75ar 47514 tr 1 47524 752m 47519 hlt j 0451 47524 tra i 02 47429 74kr 47529 rcv u 0306 47534 tr 1 01 00204 02 4 47539 tr 1 47554 755m to next routine 7 2 005 47544 451 s 2 001 47545 | 3 47549 47459 745r 7 7 routine #452 7 test sb 08 for false 900 7 or 901 checks. 7 47554 sb % 08 47681 7o8j 47559 trs o 10 47614 7ojm 47564 trs o 11 47614 7oam 7 47569 set b 01 00001 00 1 47574 lod 8 01 47681 76yj sbr char 0 red. 47579 trs o 11 47584 7nhm 47584 sb % 09 47683 7oyl do sb with sbr red. 47589 trs o 11 47614 7oam and test 901 7 47594 set b 01 00000 00 0 reset good 47599 sb % 09 47681 7oyj 47604 trs o 11 47609 7o+r 47609 tr 1 47659 765r 7 47614 set b 01 00000 00 0 reset error 47619 sb % 09 47681 7oyj 47624 trs o 11 47629 7obr 7 47629 tra i 01 47659 76vr error routine 47634 Sel 2 0500 47639 wr r 47675 767n 47644 tra i 03 47654 76em 47649 tr 1 47659 765r 47654 hlt j 0452 47659 tra i 02 47554 75nm 47664 rcv u 0306 47669 tr 1 01 00204 02 4 47674 tr 1 47689 768r to next routine 7 2 005 47679 452 s 2 001 47680 | 2 003 47683 x 7 7 7 routine #453 7 test bl ad trigger on 7 sb instruction. test false 7 tn of any trigger in sb 08. 7 47689 set b 0001 47694 lod 8 47819 781r 47699 sb % 08 47704 7p0m 47704 sb % 09 47824 7qsm force 900 check 47709 trs o 10 47714 7pjm 47714 unl 7 47704 770m 47719 trs o 11 47764 7pfm test 901 7 47724 tra i 47729 772r 47729 lod 8 47822 782k 47734 sb % 08 47820 7q2- 47739 sb % 08 47820 7q2- force 901, should not tn any 47744 unl 7 47820 782- 47749 trs o 11 47754 7pem 47754 tra i 47764 776m test any 47759 tr 1 47794 779m 7 47764 tra i 01 47794 77zm error routine 47769 Sel 2 0500 47774 wr r 47810 781- 47779 tra i 03 47789 77hr 47784 tr 1 47794 779m 47789 hlt j 0453 47794 tra i 02 47689 76qr 47799 rcv u 0306 47804 tr 1 01 00204 02 4 47809 tr 1 47829 782r to next routine 7 2 005 47814 453 s 2 001 47815 | 3 47819 47824 782m 2 005 47824 1 1 A 7 7 routine #454 7 test bl ad trigger and 7 sup sbr check during 7 sgn instruction. 7 47829 set b 0001 47834 lod 8 47939 793r 47839 sb % 08 47859 7q5r make red. sgn operation 47844 set b 01 00001 00 1 47849 lod 8 01 47859 78vr storage and sbr char. 0 red 47854 trs o 11 47859 7qer 7 47859 sgn t 01 47944 79um force 900 check 47864 trs o 10 47869 7qor 47869 unl 7 47859 785r 47874 trs o 11 47884 7qhm test 901 47879 tr 1 47914 791m 7 47884 tra i 01 47914 79/m error routine 47889 Sel 2 0500 47894 wr r 47930 793- 47899 tra i 03 47909 79+r 47904 tr 1 47914 791m 47909 hlt j 0454 47914 tra i 02 47829 78kr 47919 rcv u 0306 47924 tr 1 01 00204 02 4 47929 tr 1 47949 794r to next routine 7 2 005 47934 454 s 2 001 47935 | 3 47939 47944 794m 2 005 47944 xxxx1 7 --- 7Page 47-80 292-325 35 47949 tr 1 53614 t61m 7 7 routine #489 7 mpy and divide exercise. 7 mpy 9 x 1. divide 09 by 1. 7 this routine is oriented 7 towards channel operation. 7 53614 eem 3 14 00000 0+-0 53619 set b 01 00000 00 0 53624 set b 01 00100 01 0 set up ntr loop in asu 01 7 53629 spc , 0007 put spc on 0007 53634 rad h 53786 t78o rad +9 53639 mpy v 53790 t79- mpy by +1 53644 cmp 4 53788 t78q cmp answer 09 53649 tre l 53659 t65r 53654 tr 1 53739 t73r 53659 shr c 0128 shr to multiplier 53664 sub p 53786 t78o sub +9 53669 trz n 53679 t67r test zero 53674 tr 1 53739 t73r 7 53679 rad h 53792 t79k rad +09 53684 div w 53790 t79- div by +1 53689 cmp 4 53796 t79o 53694 tre l 53739 t73r check quotient 53699 cmp 4 53788 t78q of 9 53704 tre l 53714 t71m 53709 tr 1 53739 t73r 53714 shr c 0127 shr to remainder 53719 trz n 53729 t72r and test zero 53724 tr 1 53739 t73r 7 53729 ntr x 01 53629 t6sr repeate 99 more times 53734 tr 1 53769 t76r 7 53739 tra i 01 53769 t7wr error routine 53744 Sel 2 0500 53749 wr r 53793 t79l 53754 tra i 03 53764 t7fm 53759 tr 1 53769 t76r 53764 hlt j 0489 53769 tra i 02 53614 t6jm 53774 rcv u 0306 53779 tr 1 01 00204 02 4 53784 tr 1 53804 t80m to next routine 7 2 002 53786 I 2 002 53788 09 2 002 53790 A 2 002 53792 0I 2 003 53795 489 2 001 53796 | 7 7 end of program pass 7 test 914 and 916 switches 7 if 914 off, leave program 7 if 914 on, count passes and 7 repeat program. 7 if 916 off, reset channels 7 if 916 on, start channels 7 53804 eem 3 14 00000 0+-0 53809 spc , 0000 53814 rad h 54048 u04q rad pass count 53819 add g 54050 u05- add 1 to pass count 53824 set b 0002 53829 trz n 53839 t83r 53834 tr 1 53849 t84r 53839 sel 2 0500 53844 wr r 54052 u05k typeout z 53849 set b 0003 53854 st f 54048 u04q 53859 tra i 04 53884 ty8m 914 switch 53864 lim , 07 00000 0 +0 if 914 switch is off,reset also 53869 chr 3 13 00000 0+ 0 channels and associated 53874 chr 3 13 00000 0+ 0 interrupts , and leave 53879 tr 1 18219 y219 program 7 53884 set b 0001 53889 tra i 06 53939 tzlr 916 switch 53894 lim , 07 00000 0 +0 if 916 is off 53899 chr 3 13 00000 0+ 0 reset channel 53904 chr 3 13 00000 0+ 0 and bypass switches 53909 lod 8 54050 u05- a 53914 unl 7 53935 t93n set sw to nop 53919 unl 7 31560 a560 set byp sw in rout. 340 to nop 53924 unl 7 41805 180n set byp sw in rout. 419 to nop 53929 unl 7 46750 675- set byp sw in rout. 446 to nop 53934 tr 1 54044 u04m 7 53939 nop a 54044 u04m sw equals nop first time 53944 lod 8 54051 u05j 1 53949 unl 7 53935 t93n set sw to tr 53954 unl 7 31560 a560 set byp sw in rout. 340 to tr 53959 unl 7 41805 180n set byp sw in rout. 419 to tr 53964 unl 7 46750 675- set byp sw in rout. 446 to tr 53969 unl 7 54069 u06r set tape addresses 53974 unl 7 54119 u11r to 01 on 53979 unl 7 54169 u16r all four 53984 unl 7 54219 u21r channels 53989 set b 0200 set up 53994 rcv u 60004 -00m 2000 characters 53999 snd / 59804 z80m write field for 54004 snd / 59804 z80m all channels 54009 set b 0001 54014 lod 8 59795 z79n 54019 unl 7 62000 k00- 7 54024 tip , 14 54059 u+nr go start channel 20 if ready 54029 tip , 14 54109 ua-r go start channel 21 if ready 54034 tip , 14 54159 uanr go start channel 22 if ready 54039 tip , 14 54209 ub-r go start channel 23 if ready 54044 tr 1 0404 transfer to routine #001 7 2 008 54052 x00+xa1z 2 001 54053 | 7 7 channel program 7 initial test for ready 7 test each channel for 7 ready on tape #1 to #9. 7 54059 set b 01 00002 00 2 test chan 20 rdy 54064 lod 8 01 54069 u0wr tape no. 54069 sel 2 200- 54074 trs o 01 54264 u2wm if ready, go start chan 20 54079 cmp 4 01 54256 u2vo vs 09 54084 tre l 54104 u10m 54089 add g 01 54258 u2vq +1 54094 unl 7 01 54069 u0wr 54099 tr 1 54069 u06r 54104 lip , 15 00009 0++9 do lip if no tape #01-09 ready 7 54109 set b 01 00002 00 2 test chan 21 rdy 54114 lod 8 01 54119 u1/r 54119 sel 2 210- 54124 trs o 01 54924 u9sm if ready, go start chan 21 54129 cmp 4 01 54256 u2vo 54134 tre l 54154 u15m 54139 add g 01 54258 u2vq 54144 unl 7 01 54119 u1/r 54149 tr 1 54119 u11r 54154 lip , 15 00009 0++9 7 54159 set b 01 00002 00 2 test chan 22 rdy 54164 lod 8 01 54169 u1wr 54169 sel 2 220- 54174 trs o 01 55584 v5ym if ready, go start chan 22 54179 cmp 4 01 54256 u2vo 54184 tre l 54204 u20m 54189 add g 01 54258 u2vq 54194 unl 7 01 54169 u1wr 54199 tr 1 54169 u16r 54204 lip , 15 00009 0++9 7 54209 set b 01 00002 00 2 test chan 23 rdy 54214 lod 8 01 54219 u2/r 54219 sel 2 230- 54224 trs o 01 56244 w2um if ready, go start chan 22 54229 cmp 4 01 54256 u2vo 54234 tre l 54254 u25m 54239 add g 01 54258 u2vq 54244 unl 7 01 54219 u2/r 54249 tr 1 54219 u21r 54254 lip , 15 00009 0++9 7 2 004 54258 09xa 7 7 interrupt program 7 for channel 20 page 1 7 wr, bsp, rd on channel 20. 7 check for false interrupts, 7 channel checks, and compare 7 write and read fields. 7 54264 unl 7 01 54299 u2zr 54269 unl 7 01 54324 u3sm set up 54274 unl 7 01 54354 u3vm select 54279 unl 7 01 54389 u3yr 54284 eim , 06 00000 0 -0 54289 skp 3 0009 initial skip to put tape 54294 lip , 15 02000 2++0 head in proper record gap. 54299 sel 2 200- 54304 trs o 54469 u46r test for end of file 54309 wr r 60000 -00- write 2000 characters 54314 lip , 15 02000 2++0 7 7 backspace 54319 nop a 54299 u29r 54324 sel 2 200- 54329 trs o 01 54339 u3tr test ready after interrupt 54334 tr 1 54534 u53m 54339 trs o 02 54549 u5mr test for write chk 54344 bsp 3 0004 54349 lip , 15 02000 2++0 7 7 read 2000 characters 54354 sel 2 200- 54359 trs o 01 54369 u3wr test ready after interrupt 54364 tr 1 54564 u56m 54369 rcv u 62009 k00r 54374 blm $ 0402 clear read field 54379 rd y 62005 k00n 54384 lip , 15 02000 2++0 7 7 compare wr and rd fields 54389 sel 2 200- 54394 trs o 01 54404 u4 m test ready after interrupt 54399 tr 1 54579 u57r 54404 trs o 02 54594 u5rm test for rd chk 54409 set b 02 00200 02-0 54414 lod 8 02 59999 z9rr lod 200 characters 54419 lda = 01 59759 z7vr 54424 ula * 01 54429 u4sr 54429 cmp 4 02 62204 k2-m cmp 200 char. 54434 trs o 11 54609 uo+r test 901 54439 tre l 54449 u44r test equal 54444 tr 1 54609 u60r 54449 cmp 4 01 59755 z7vn cmp equal at end of read field 54454 tre l 54299 u29r 54459 add g 01 59794 z7zm add 200 to 54464 tr 1 54424 u42m cmp address 7 7 7 interrupt program 7 for channel 20 page 2 7 rewind and error typeouts 54469 iof 3 0000 54474 rwd 3 0002 if end off file. 54479 set b 01 00002 00 2 rewind tape and 54484 lod 8 01 54299 u2zr find next ready tape. 54489 cmp 4 01 54762 u7wk 54494 tre l 54509 u50r 54499 add g 01 54764 u7wm 54504 tr 1 54514 u51m 54509 lod 8 01 54760 u7w- 54514 unl 7 01 54519 u5/r 54519 sel 2 200- 54524 trs o 01 54264 u2wm 54529 tr 1 54489 u48r 7 54534 set b 01 00008 00 8 lod tr address and 54539 lod 8 01 54627 u6sp t/o address according 54544 tr 1 54674 u67m to error which occured 54549 set b 01 00008 00 8 54554 lod 8 01 54635 u6tn 54559 tr 1 54674 u67m 54564 set b 01 00008 00 8 54569 lod 8 01 54643 u6ul 54574 tr 1 54674 u67m 54579 set b 01 00008 00 8 54584 lod 8 01 54651 u6vj 54589 tr 1 54674 u67m 54594 set b 01 00008 00 8 54599 lod 8 01 54659 u6vr 54604 tr 1 54674 u67m 54609 set b 01 00008 00 8 54614 lod 8 01 54667 u6wp 54619 tr 1 54674 u67m 7 3 54623 54339 u33r 3 54627 54765 u76n 3 54631 54344 u34m 3 54635 54853 u85l 3 54639 54369 u36r 3 54643 54794 u79m 3 54647 54404 u40m 3 54651 54824 u82m 3 54655 54409 u40r 3 54659 54873 u87l 3 54663 54299 u29r 3 54667 54893 u89l 7 7 interrupt program 7 for channel 20 page 3 7 error typeouts chan 20 54674 unl 7 01 54758 u7vq unl tr address 54679 tra i 01 54754 u7vm 54684 set b 01 00004 00 4 54689 unl 7 01 54729 u7sr unl t/o address 54694 set b 01 00001 00 1 54699 lod 8 01 54299 u2zr tape no. 54704 unl 7 01 54871 u8xj 54709 unl 7 01 54891 u8zj 54714 unl 7 01 54915 u9/n 54719 unl 7 01 54749 u7ur 7 54724 sel 2 0500 do typeout 54729 wr r 0000 54734 tra i 03 54744 u7dm 54739 tr 1 54749 u74r 54744 hlt j 2000 54749 sel 2 200- reselect tape 54754 tr 1 0000 do typeout 7 7 constants + typeouts 2 004 54758 2 006 54764 0109 A 2 028 54792 int 200 after wr and not rdy 2 001 54793 | 2 029 54822 int 200 after bsp and not rdy 2 001 54823 | 2 028 54851 int 200 after rd and not rdy 2 001 54852 | 2 019 54871 chan chk on wr 200x 2 001 54872 | 2 019 54891 chan chk on rd 200x 2 001 54892 | 2 024 54916 rd-wr data unequal 200x 2 001 54917 | 7 7 interrupt program 7 for channel 21 page 1 7 wr, bsp, rd on channel 21. 7 check for false interrupts, 7 channel checks, and compare 7 write and read fields. 7 54924 unl 7 01 54959 u9vr 54929 unl 7 01 54984 u9ym set up 54934 unl 7 01 55014 v0/m select 54939 unl 7 01 55049 v0ur 54944 eim , 06 00000 0 -0 54949 skp 3 0009 initial skip to put tape 54954 lip , 15 02100 2A+0 head in proper record gap. 54959 sel 2 210- 54964 trs o 55129 v12r test for end of file 54969 wr r 60000 -00- write 2000 characters 54974 lip , 15 02100 2A+0 7 7 backspace 54979 nop a 54959 u95r 54984 sel 2 210- 54989 trs o 01 54999 u9zr test ready after interrupt 54994 tr 1 55194 v19m 54999 trs o 02 55209 v2-r test for write chk 55004 bsp 3 0004 55009 lip , 15 02100 2a+0 7 7 read 2000 characters 55014 sel 2 210- 55019 trs o 01 55029 v0sr test ready after interrupt 55024 tr 1 55224 v22m 55029 rcv u 64029 m02r 55034 blm $ 0402 clear rd field 55039 rd y 64025 m02n 55044 lip , 15 02100 2a+0 7 7 compare wr and rd fields 55049 sel 2 210- 55054 trs o 01 55064 v0wm test ready after interrupt 55059 tr 1 55239 v23r 55064 trs o 02 55254 v2nm test for rd chk 55069 set b 02 00200 02-0 55074 lod 8 02 59999 z9rr lod 200 characters 55079 lda = 01 59769 z7wr 55084 ula * 01 55089 v0yr 55089 cmp 4 02 64224 m2km cmp 200 char. 55094 trs o 11 55269 vkfr test 901 55099 tre l 55109 v10r test equal 55104 tr 1 55269 v26r 55109 cmp 4 01 59765 z7wn cmp equal at end of read field 55114 tre l 54959 u95r 55119 add g 01 59794 z7zm add 200 to 55124 tr 1 55084 v08m cmp address 7 7 7 interrupt program 7 for channel 21 page 2 7 rewind and error typeouts 55129 iof 3 0000 55134 rwd 3 0002 if end off file. 55139 set b 01 00002 00 2 rewind tape and 55144 lod 8 01 54959 u9vr find next ready tape. 55149 cmp 4 01 55422 v4sk 55154 tre l 55169 v16r 55159 add g 01 55424 v4sm 55164 tr 1 55174 v17m 55169 lod 8 01 55420 v4s- 55174 unl 7 01 55179 v1xr 55179 sel 2 210- 55184 trs o 01 54924 u9sm 55189 tr 1 55149 v14r 7 55194 set b 01 00008 00 8 lod tr address and 55199 lod 8 01 55287 v2yp t/o address according 55204 tr 1 55334 v33m to error which occured 55209 set b 01 00008 00 8 55214 lod 8 01 55295 v2zn 55219 tr 1 55334 v33m 55224 set b 01 00008 00 8 55229 lod 8 01 55303 v3 l 55234 tr 1 55334 v33m 55239 set b 01 00008 00 8 55244 lod 8 01 55311 v3/j 55249 tr 1 55334 v33m 55254 set b 01 00008 00 8 55259 lod 8 01 55319 v3/r 55264 tr 1 55334 v33m 55269 set b 01 00008 00 8 55274 lod 8 01 55327 v3sp 55279 tr 1 55334 v33m 7 3 55283 54999 u99r 3 55287 55425 v42n 3 55291 55004 v00m 3 55295 55513 v51l 3 55299 55029 v02r 3 55303 55454 v45m 3 55307 55064 v06m 3 55311 55484 v48m 3 55315 55069 v06r 3 55319 55533 v53l 3 55323 54959 u95r 3 55327 55553 v55l 7 7 interrupt program 7 for channel 21 page 3 7 error typeouts chan 21 55334 unl 7 01 55418 v4/q unl tr address 55339 tra i 01 55414 v4/m 55344 set b 01 00004 00 4 55349 unl 7 01 55389 v3yr unl t/o address 55354 set b 01 00001 00 1 55359 lod 8 01 54959 u9vr tape no. 55364 unl 7 01 55531 v5tj 55369 unl 7 01 55551 v5vj 55374 unl 7 01 55575 v5xn 55379 unl 7 01 55409 v4 r 7 55384 sel 2 0500 do typeout 55389 wr r 0000 55394 tra i 03 55404 v4+m 55399 tr 1 55409 v40r 55404 hlt j 2100 55409 sel 2 210- reselect tape 55414 tr 1 0000 do typeout 7 7 constants + typeouts 2 004 55418 2 006 55424 0109 A 2 028 55452 int 210 after wr and not rdy 2 001 55453 | 2 029 55482 int 210 after bsp and not rdy 2 001 55483 | 2 028 55511 int 210 after rd and not rdy 2 001 55512 | 2 019 55531 chan chk on wr 210x 2 001 55532 | 2 019 55551 chan chk on rd 210x 2 001 55552 | 2 024 55576 rd-wr data unequal 210x 2 001 55577 | 7 7 interrupt program 7 for channel 22 page 1 7 wr, bsp, rd on channel 22. 7 check for false interrupts, 7 channel checks, and compare 7 write and read fields. 7 55584 unl 7 01 55619 v6/r 55589 unl 7 01 55644 v6um set up 55594 unl 7 01 55674 v6xm select 55599 unl 7 01 55709 v7 r 55604 eim , 06 00000 0 -0 55609 skp 3 0009 initial skip to put tape 55614 lip , 15 02200 2b+0 head in proper record gap. 55619 sel 2 220- 55624 trs o 55789 v78r test for end of file 55629 wr r 60000 -00- write 2000 characters 55634 lip , 15 02200 2b+0 7 7 backspace 55639 nop a 55619 v61r 55644 sel 2 220- 55649 trs o 01 55659 v6vr test ready after interrupt 55654 tr 1 55854 v85m 55659 trs o 02 55869 v8or test for write chk 55664 bsp 3 0004 55669 lip , 15 02200 2b+0 7 7 read 2000 characters 55674 sel 2 220- 55679 trs o 01 55689 v6yr test ready after interrupt 55684 tr 1 55884 v88m 55689 rcv u 66049 o04r 55694 blm $ 0402 clear rd field 55699 rd y 66045 o04n 55704 lip , 15 02200 2b+0 7 7 compare wr and rd fields 55709 sel 2 220- 55714 trs o 01 55724 v7sm test ready after interrupt 55719 tr 1 55899 v89r 55724 trs o 02 55914 v9jm test for rd chk 55729 set b 02 00200 02-0 55734 lod 8 02 59999 z9rr lod 200 characters 55739 lda = 01 59779 z7xr 55744 ula * 01 55749 v7ur 55749 cmp 4 02 66244 o2mm cmp 200 char. 55754 trs o 11 55929 vrbr test 901 55759 tre l 55769 v76r test equal 55764 tr 1 55929 v92r 55769 cmp 4 01 59775 z7xn cmp equal at end of read field 55774 tre l 55619 v61r 55779 add g 01 59794 z7zm add 200 to 55784 tr 1 55744 v74m cmp address 7 7 7 interrupt program 7 for channel 22 page 2 7 rewind and error typeouts 55789 iof 3 0000 55794 rwd 3 0002 if end off file. 55799 set b 01 00002 00 2 rewind tape and 55804 lod 8 01 55619 v6/r find next ready tape. 55809 cmp 4 01 56082 w0yk 55814 tre l 55829 v82r 55819 add g 01 56084 w0ym 55824 tr 1 55834 v83m 55829 lod 8 01 56080 w0y- 55834 unl 7 01 55839 v8tr 55839 sel 2 220- 55844 trs o 01 55584 v5ym 55849 tr 1 55809 v80r 7 55854 set b 01 00008 00 8 lod tr address and 55859 lod 8 01 55947 v9up t/o address according 55864 tr 1 55994 v99m to error which occured 55869 set b 01 00008 00 8 55874 lod 8 01 55955 v9vn 55879 tr 1 55994 v99m 55884 set b 01 00008 00 8 55889 lod 8 01 55963 v9wl 55894 tr 1 55994 v99m 55899 set b 01 00008 00 8 55904 lod 8 01 55971 v9xj 55909 tr 1 55994 v99m 55914 set b 01 00008 00 8 55919 lod 8 01 55979 v9xr 55924 tr 1 55994 v99m 55929 set b 01 00008 00 8 55934 lod 8 01 55987 v9yp 55939 tr 1 55994 v99m 7 3 55943 55659 v65r 3 55947 56085 w08n 3 55951 55664 v66m 3 55955 56173 w17l 3 55959 55689 v68r 3 55963 56114 w11m 3 55967 55724 v72m 3 55971 56144 w14m 3 55975 55729 v72r 3 55979 56193 w19l 3 55983 55619 v61r 3 55987 56213 w21l 7 7 interrupt program 7 for channel 22 page 3 7 error typeouts chan 22 55994 unl 7 01 56078 w0xq unl tr address 55999 tra i 01 56074 w0xm 56004 set b 01 00004 00 4 56009 unl 7 01 56049 w0ur unl t/o address 56014 set b 01 00001 00 1 56019 lod 8 01 55619 v6/r tape no. 56024 unl 7 01 56191 w1zj 56029 unl 7 01 56211 w2/j 56034 unl 7 01 56235 w2tn 56039 unl 7 01 56069 w0wr 7 56044 sel 2 0500 do typeout 56049 wr r 0000 56054 tra i 03 56064 w0fm 56059 tr 1 56069 w06r 56064 hlt j 2200 56069 sel 2 220- reselect tape 56074 tr 1 0000 do typeout 7 7 constants + typeouts 2 004 56078 2 006 56084 0109 A 2 028 56112 int 220 after wr and not rdy 2 001 56113 | 2 029 56142 int 220 after bsp and not rdy 2 001 56143 | 2 028 56171 int 220 after rd and not rdy 2 001 56172 | 2 019 56191 chan chk on wr 220x 2 001 56192 | 2 019 56211 chan chk on rd 220x 2 001 56212 | 2 024 56236 rd-wr data unequal 220x 2 001 56237 | 7 7 interrupt program 7 for channel 23 page 1 7 wr, bsp, rd on channel 23. 7 check for false interrupts, 7 channel checks, and compare 7 write and read fields. 7 56244 unl 7 01 56279 w2xr 56249 unl 7 01 56304 w3 m set up 56254 unl 7 01 56334 w3tm select 56259 unl 7 01 56369 w3wr 56264 eim , 06 00000 0 -0 56269 skp 3 0009 initial skip to put tape 56274 lip , 15 02300 2c+0 head in proper record gap. 56279 sel 2 230- 56284 trs o 56449 w44r test for end of file 56289 wr r 60000 -00- write 2000 characters 56294 lip , 15 02300 2c+0 7 7 backspace 56299 nop a 56279 w27r 56304 sel 2 230- 56309 trs o 01 56319 w3/r test ready after interrupt 56314 tr 1 56514 w51m 56319 trs o 02 56529 w5kr test for write chk 56324 bsp 3 0004 56329 lip , 15 02300 2c+0 7 7 read 2000 characters 56334 sel 2 230- 56339 trs o 01 56349 w3ur test ready after interrupt 56344 tr 1 56544 w54m 56349 rcv u 68069 q06r 56354 blm $ 0402 clear rd field 56359 rd y 68065 q06n 56364 lip , 15 02300 2c+0 7 7 compare wr and rd fields 56369 sel 2 230- 56374 trs o 01 56384 w3ym test ready after interrupt 56379 tr 1 56559 w55r 56384 trs o 02 56574 w5pm test for rd chk 56389 set b 02 00200 02-0 56394 lod 8 02 59999 z9rr lod 200 characters 56399 lda = 01 59789 z7yr 56404 ula * 01 56409 w4 r 56409 cmp 4 02 68264 q2om cmp 200 char. 56414 trs o 11 56589 wnhr test 901 56419 tre l 56429 w42r test equal 56424 tr 1 56589 w58r 56429 cmp 4 01 59785 z7yn cmp equal at end of read field 56434 tre l 56279 w27r 56439 add g 01 59794 z7zm add 200 to 56444 tr 1 56404 w40m cmp address 7 7 7 interrupt program 7 for channel 23 page 2 7 rewind and error typeouts 56449 iof 3 0000 56454 rwd 3 0002 if end off file. 56459 set b 01 00002 00 2 rewind tape and 56464 lod 8 01 56279 w2xr find next ready tape. 56469 cmp 4 01 56742 w7uk 56474 tre l 56489 w48r 56479 add g 01 56744 w7um 56484 tr 1 56494 w49m 56489 lod 8 01 56740 w7u- 56494 unl 7 01 56499 w4zr 56499 sel 2 230- 56504 trs o 01 56244 w2um 56509 tr 1 56469 w46r 7 56514 set b 01 00008 00 8 lod tr address and 56519 lod 8 01 56607 w6 p t/o address according 56524 tr 1 56654 w65m to error which occured 56529 set b 01 00008 00 8 56534 lod 8 01 56615 w6/n 56539 tr 1 56654 w65m 56544 set b 01 00008 00 8 56549 lod 8 01 56623 w6sl 56554 tr 1 56654 w65m 56559 set b 01 00008 00 8 56564 lod 8 01 56631 w6tj 56569 tr 1 56654 w65m 56574 set b 01 00008 00 8 56579 lod 8 01 56639 w6tr 56584 tr 1 56654 w65m 56589 set b 01 00008 00 8 56594 lod 8 01 56647 w6up 56599 tr 1 56654 w65m 7 3 56603 56319 w31r 3 56607 56745 w74n 3 56611 56324 w32m 3 56615 56833 w83l 3 56619 56349 w34r 3 56623 56774 w77m 3 56627 56384 w38m 3 56631 56804 w80m 3 56635 56389 w38r 3 56639 56853 w85l 3 56643 56279 w27r 3 56647 56873 w87l 7 7 interrupt program 7 for channel 23 page 3 7 error typeouts chan 23 56654 unl 7 01 56738 w7tq unl tr address 56659 tra i 01 56734 w7tm 56664 set b 01 00004 00 4 56669 unl 7 01 56709 w7 r unl t/o address 56674 set b 01 00001 00 1 56679 lod 8 01 56279 w2xr tape no. 56684 unl 7 01 56851 w8vj 56689 unl 7 01 56871 w8xj 56694 unl 7 01 56895 w8zn 56699 unl 7 01 56729 w7sr 7 56704 sel 2 0500 do typeout 56709 wr r 0000 56714 tra i 03 56724 w7bm 56719 tr 1 56729 w72r 56724 hlt j 2300 56729 sel 2 230- reselect tape 56734 tr 1 0000 do typeout 7 7 constants + typeouts 2 004 56738 2 006 56744 0109 A 2 028 56772 int 230 after wr and not rdy 2 001 56773 | 2 029 56702 int 220 after bsp and not rdy 2 001 56703 | 2 028 56731 int 230 after rd and not rdy 2 001 56732 | 2 019 56751 chan chk on wr 230x 2 001 56752 | 2 019 56771 chan chk on rd 230x 2 001 56772 | 2 024 56796 rd-wr data unequal 230x 2 001 56797 | 2 006 59755 064004 3 59759 62204 k20m start of chan 20 rd field 2 006 59765 066024 3 59769 64224 m22m start of chan 21 rd field 2 006 59775 068044 3 59779 66244 o24m start of chan 22 rd field 2 006 59785 070064 3 59789 68264 q26m start of chan 23 rd field 2 005 59794 xx20+ 2 001 59795 00 | 2 004 59799 2 040 59839 aaaaabbbbbcccccdddddeeeeefffffgggggghhhhhh 2 040 59879 iiiiijjjjjkkkkklllllmmmmmnnnnnoooooopppppp 2 040 59919 qqqqqrrrrrssssstttttuuuuuvvvvvwwwwwwxxxxxx 2 040 59959 yyyyyzzzzz00000111112222233333444444555555 2 040 59999 66666777778888899999@@@@@/////$$$$$$...... 5 500 60499 write 5 500 60999 field 5 500 61499 for all 5 500 61999 channels 2 001 62000 | 2 004 62004 5 800 62804 read field 5 800 63504 for 5 400 64004 channel 20 2 020 64024 5 800 64824 read field 5 800 65624 for 5 400 66024 channel 21 2 020 66044 5 800 66844 read field 5 800 67644 for 5 400 68044 channel 22 2 020 68064 5 800 68864 read field 5 800 69664 for 5 400 70064 channel 23 2 020 70084