IBM 1410/7010 Programmers Model
The 1410 and 7010 were redesigned 1401's with out the bit encoding on the instruction set, and many of the extensions to the 1401 were standard on the 1410. The major difference between the 1410 and the 7010 was that the 7010 had 4 channels while the 1410 had 2. The 7010 read/wrote memory 2 characters at a time and optional could have floating point. Other then that the machines were identical. Also the 1410 could only address 80k of memory while the 7010 could address the full 100k of memory. I will refer to them both as 7010.
The 7010 had no registers to speak of. All operands where fields in memory. The machine at an instruction pointer register, and six registered labeled A through H which could be stored into memory only. A and B held the last address accessed after an instruction, C and D were special purpose registers. E, F, G, H help the last address accessed by the channel 1 through 4. All registers where 5 characters long.
Each memory location was 6 bits wide with a parity bit and a word mark bit. The word mark was used to indicate end of field. Generaly fields started in high memory and worked towards low memory. Numbers were represented by low order 4 bits of character. For the first character of a numeric field the 2 high order digits (zone), were the sign (10 for minus) (- char) other wise they were considered positive. Whenever the machine changed the sign positive was always represented as (11) (+ char).
Instructions consisted of a single character, followed by up to two addresses of 5 characters each and an optional modifier character. For I/O operations the first address was 3 characters and specified the channel, and device. Any of the addresses or modifer could be omited and the last values would be used, this was called chaining. The machine required that the character after the last character of an instruction and the opcode of the instruction both have the word mark set. This was how the machine determined when it had fetched a full instruction.
Zone bits over the hundreds and tens digit were used to indicated indexed addressing. Each register was located in memory and was 5 characters long. These were added or subtracted from the address to give the actual address. The address was wrapped around so adding large value was same as subtracting smaller value.
| Hundreds Zone | Tens Zone | Index | Memory |
| 00 | 00 | No index | |
| 00 | 01 | 1 | 25 |
| 00 | 10 | 2 | 30 |
| 00 | 11 | 3 | 35 |
| 01 | 00 | 4 | 40 |
| 01 | 01 | 5 | 45 |
| 01 | 10 | 6 | 50 |
| 01 | 11 | 7 | 55 |
| 10 | 00 | 8 | 60 |
| 10 | 01 | 9 | 65 |
| 10 | 10 | 10 | 70 |
| 10 | 11 | 11 | 75 |
| 11 | 00 | 12 | 80 |
| 11 | 01 | 13 | 85 |
| 11 | 10 | 14 | 90 |
| 11 | 11 | 15 | 95 |
Floating point operations used a floating point accumulator that was located at address 290.
The operations were as follows:
Opcode Desc Code Form
Modifiers A Add A A aaaaa bbbbb S Subtract S S aaaaa bbbbb ZA Zero and Add ? ? aaaaa bbbbb ZS Zero and Subtract ? ! aaaaa bbbbb M Multiply ' ' aaaaa bbbbb D Divide ( ( aaaaa bbbbb SAR Store Address Register G G ccccc m Register SWM Set Word Mark , , aaaaa bbbbb CWM Clear Word Mark ) ) aaaaa bbbbb CS Clear Storage / / aaaaa bbbbb H Halt . . aaaaa N Nop N N any length MSZ Move Suppress Zero Z Z aaaaa bbbbb C Compare C C aaaaa bbbbb MCE Move and Edit C E aaaaa bbbbb BCE Branch Character Equal B B aaaaa bbbbb c Character BBE Branch Bit Equal W W aaaaa bbbbb c Mask BWE Branch Word Equal V
V aaaaa bbbbb c Flags
bit 1 - WM
bit 2 - ZonesM* Move/Scan
D D aaaaa bbbbb m
bit encoded.
1 bit - numeric
2 bit - zone
4 bit - word mark
8 bit - Left/Right
A/B bit - ending
*
LL
LE
LLE
LH
LLH
LEH
*Table Lookup T
T aaaaa bbbbb m Match
blank never
1 <
2 =
3 ≤
4 >
5 ≠
6 ≥
7 anyB
BU
BE
BL
BH
BZ
BAV
BDV
BXO
BXU
BOL1
BOL2
BOL3
BOL4
BB1
BB2
BPCB1
BPCB2
BCV1
BCV2
BC91
BC92
Branch J
J aaaaa blank
J aaaaa /
J aaaaa S
J aaaaa T
J aaaaa U
J aaaaa V
J aaaaa Z
J aaaaa W
J aaaaa Y
J aaaaa X
J aaaaa 1
J aaaaa 2
3 aaaaa 4
J aaaaa M
J aaaaa (
J aaaaa R
J aaaaa L
J aaaaa -
J aaaaa )
J aaaaa 9
J aaaaa -0Condition
FRA
FST
FA
FS
FM
FD
Floating Point
Reset Add
Store
Add
Subtract
Multiply
Divide= = aaaaa m
= aaaaa R
= aaaaa L
= aaaaa A
= aaaaa S
= aaaaa M
= aaaaa DType STATS
STCPU
RSCPUStore Status
7010 only$ $ ccccc m
$ ccccc S
$ ccccc R
channel BEX
BNR
BCB
BER
BEF
BNT
BWLBranch Channel
R - Channel 1
X - Channel 2
3 - Channel 3
1 - Channel 4o aaaaa m
o aaaaa 1
o aaaaa 2
o aaaaa 4
o aaaaa 8
o aaaaa T
o aaaaa -Bit Mask
1 Not Ready
2 Busy
4 Error
8 EOF
A No Transfer
B Wrong LenghtCC Carrage Control
F - Channel 1
2 - Channel 2
F m
2 mControl SSF Stacker Control
K - Channel 1
4 - Channel 2
K m
4 mControl BPI Priority control Y Y aaaaa m
Function
BSP
SKP
WTM
RWD
RWU
Tape Control U U c f d
U c B d
U c E d
U c M d
U c R d
U c U d
c channel
d device* Load Mode L L c f d bbbbb m
c channel
f unit
d device
m - read/write* Move Mode M M c f d bbbbb m
c channel
f unit
d device
m - read/write