IBM 1410/7010 Programmers Model

The 1410 and 7010 were redesigned 1401's with out the bit encoding on the instruction set, and many of the extensions to the 1401 were standard on the 1410. The major difference between the 1410 and the 7010 was that the 7010 had 4 channels while the 1410 had 2. The 7010 read/wrote memory 2 characters at a time and optional could have floating point. Other then that the machines were identical. Also the 1410 could only address 80k of memory while the 7010 could address the full 100k of memory. I will refer to them both as 7010.

The 7010 had no registers to speak of. All operands where fields in memory. The machine at an instruction pointer register, and six registered labeled A through H which could be stored into memory only. A and B held the last address accessed after an instruction, C and D were special purpose registers. E, F, G, H help the last address accessed by the channel 1 through 4. All registers where 5 characters long.

Each memory location was 6 bits wide with a parity bit and a word mark bit. The word mark was used to indicate end of field. Generaly fields started in high memory and worked towards low memory. Numbers were represented by low order 4 bits of character. For the first character of a numeric field the 2 high order digits (zone), were the sign (10 for minus) (- char) other wise they were considered positive. Whenever the machine changed the sign positive was always represented as (11) (+ char).

Instructions consisted of a single character, followed by up to two addresses of 5 characters each and an optional modifier character. For I/O operations the first address was 3 characters and specified the channel, and device. Any of the addresses or modifer could be omited and the last values would be used, this was called chaining. The machine required that the character after the last character of an instruction and the opcode of the instruction both have the word mark set. This was how the machine determined when it had fetched a full instruction.

Zone bits over the hundreds and tens digit were used to indicated indexed addressing. Each register was located in memory and was 5 characters long. These were added or subtracted from the address to give the actual address. The address was wrapped around so adding large value was same as subtracting smaller value.

Hundreds ZoneTens ZoneIndexMemory
0000No index 
0001125
0010230
0011335
0100440
0101545
0110650
0111755
1000860
1001965
10101070
10111175
11001280
11011385
11101490
11111595

Floating point operations used a floating point accumulator that was located at address 290.

The operations were as follows:

OpcodeDescCodeForm Modifiers
AAddAA aaaaa bbbbb 
SSubtractSS aaaaa bbbbb 
ZAZero and Add?? aaaaa bbbbb 
ZSZero and Subtract?! aaaaa bbbbb 
MMultiply'' aaaaa bbbbb 
DDivide(( aaaaa bbbbb 
SARStore Address RegisterGG ccccc mRegister
SWMSet Word Mark,, aaaaa bbbbb 
CWMClear Word Mark)) aaaaa bbbbb 
CSClear Storage// aaaaa bbbbb 
HHalt.. aaaaa 
NNopNN any length 
MSZMove Suppress ZeroZZ aaaaa bbbbb 
CCompareCC aaaaa bbbbb 
MCEMove and EditCE aaaaa bbbbb 
BCEBranch Character EqualBB aaaaa bbbbb cCharacter
BBEBranch Bit EqualWW aaaaa bbbbb cMask
BWEBranch Word EqualV V aaaaa bbbbb cFlags
bit 1 - WM
bit 2 - Zones
M*Move/Scan DD aaaaa bbbbb m bit encoded.
1 bit - numeric
2 bit - zone
4 bit - word mark
8 bit - Left/Right
A/B bit - ending

*
LL
LE
LLE
LH
LLH
LEH
*
Table LookupT T aaaaa bbbbb mMatch
blank never
1 <
2 =
3 ≤
4 >
5 ≠
6 ≥
7 any
B
BU
BE
BL
BH
BZ
BAV
BDV
BXO
BXU
BOL1
BOL2
BOL3
BOL4
BB1
BB2
BPCB1
BPCB2
BCV1
BCV2
BC91
BC92
BranchJ J aaaaa blank
J aaaaa /
J aaaaa S
J aaaaa T
J aaaaa U
J aaaaa V
J aaaaa Z
J aaaaa W
J aaaaa Y
J aaaaa X
J aaaaa 1
J aaaaa 2
3 aaaaa 4
J aaaaa M
J aaaaa (
J aaaaa R
J aaaaa L
J aaaaa -
J aaaaa )
J aaaaa 9
J aaaaa -0
Condition

FRA
FST
FA
FS
FM
FD
Floating Point
Reset Add
Store
Add
Subtract
Multiply
Divide
== aaaaa m
= aaaaa R
= aaaaa L
= aaaaa A
= aaaaa S
= aaaaa M
= aaaaa D
Type
STATS
STCPU
RSCPU
Store Status
7010 only
$$ ccccc m
$ ccccc S
$ ccccc R
channel
BEX
BNR
BCB
BER
BEF
BNT
BWL
Branch Channel R - Channel 1
X - Channel 2
3 - Channel 3
1 - Channel 4
o aaaaa m
o aaaaa 1
o aaaaa 2
o aaaaa 4
o aaaaa 8
o aaaaa T
o aaaaa -
Bit Mask
1 Not Ready
2 Busy
4 Error
8 EOF
A No Transfer
B Wrong Lenght
CCCarrage Control
F - Channel 1
2 - Channel 2

F m
2 m
Control
SSFStacker Control
K - Channel 1
4 - Channel 2

K m
4 m
Control
BPIPriority controlYY aaaaa m Function

BSP
SKP
WTM
RWD
RWU
Tape ControlUU c f d
U c B d
U c E d
U c M d
U c R d
U c U d
c channel
d device
*Load ModeLL c f d bbbbb m c channel
f unit
d device
m - read/write
*Move ModeMM c f d bbbbb m c channel
f unit
d device
m - read/write